| Arithmetic and Logic
Instructions |
| ADD | Rd, Rr | Add two Registers | Rd <-- Rd + Rr | Z,C,N,V,H | 1 |
| ADC | Rd, Rr | Add with Carry two Registers | Rd <-- Rd + Rr + C | Z,C,N,V,H | 1 |
| ADIW | Rdl,K | Add Immediate to Word | Rdh:Rdl <-- Rdh:Rdl + K | Z,C,N,V,S | 2 |
| SUB | Rd, Rr | Subtract two Registers | Rd <-- Rd - Rr | Z,C,N,V,H | 1 |
| SUBI | Rd, K | Subtract Constant from Register | Rd <-- Rd - K | Z,C,N,V,H | 1 |
| SBC | Rd, Rr | Subtract with Carry two Registers | Rd <-- Rd - Rr - C | Z,C,N,V,H | 1 |
| SBCI | Rd, K | Subtract with Carry Constant from Reg. | Rd <-- Rd - K - C | Z,C,N,V,H | 1 |
| SBIW | Rdl,K | Subtract Immediate from Word | Rdh:Rdl <-- Rdh:Rdl - K | Z,C,N,V,S | 2 |
| AND | Rd, Rr | Logical AND Registers | Rd <-- Rd x Rr | Z,N,V | 1 |
| ANDI | Rd, K | Logical AND Register and Constant | Rd <-- Rd x K | Z,N,V | 1 |
| OR | Rd, Rr | Logical OR Registers | Rd <-- Rd v Rr | Z,N,V | 1 |
| ORI | Rd, K | Logical OR Register and Constant | Rd <-- Rd v K | Z,N,V | 1 |
| EOR | Rd, Rr | Exclusive OR Registers | Rd _ Rd _ Rr | Z,N,V | 1 |
| COM | Rd | One’s Complement | Rd _ 0xFF - Rd | Z,C,N,V | 1 |
| NEG | Rd | Two’s Complement | Rd _ 0x00 - Rd | Z,C,N,V,H | 1 |
| SBR | Rd,K | Set Bit(s) in Register | Rd _ Rd v K | Z,N,V | 1 |
| CBR | Rd,K | Clear Bit(s) in Register | Rd _ Rd x (0xFF - K) | Z,N,V | 1 |
| INC | Rd | Increment | Rd _ Rd + 1 | Z,N,V | 1 |
| DEC | Rd | Decrement | Rd _ Rd - 1 | Z,N,V | 1 |
| TST | Rd | Test for Zero or Minus | Rd _ Rd x Rd | Z,N,V | 1 |
| CLR | Rd | Clear Register | Rd _ Rd _ Rd | Z,N,V | 1 |
| SER | Rd | Set Register | Rd _ 0xFF | None | 1 |
| MUL | Rd, Rr | Multiply Unsigned | R1:R0 _ Rd x Rr | Z,C | 2 |
| MULS | Rd, Rr | Multiply Signed | R1:R0 _ Rd x Rr | Z,C | 2 |
| MULSU | Rd, Rr | Multiply Signed with Unsigned | R1:R0 _ Rd x Rr | Z,C | 2 |
| FMUL | Rd, Rr | Fractional Multiply Unsigned | R1:R0 _ (Rd x Rr) << 1 | Z,C | 2 |
| FMULS | Rd, Rr | Fractional Multiply Signed | R1:R0 _ (Rd x Rr) << 1 | Z,C | 2 |
| FMULSU | Rd, Rr | Fractional Multiply Signed with Unsigned | R1:R0 _ (Rd x Rr) << 1 | Z,C | 2 |
| Branch Instructions |
| RJMP | k | Relative Jump | PC _ PC + k + 1 | None | 2 |
| IJMP | — | Indirect Jump to (Z) | PC _ Z | None | 2 |
| JMP | k | Direct Jump | PC _ k | None | 3 |
| RCALL | k | Relative Subroutine Call | PC _ PC + k + 1 | None | 3 |
| ICALL | — | Indirect Call to (Z) | PC _ Z | None | 3 |
| CALL | k | Direct Subroutine Call | PC _ k | None | 4 |
| RET | — | Subroutine Return | PC _ STACK | None | 4 |
| RETI | — | Interrupt Return | PC _ STACK | I | 4 |
| CPSE | Rd,Rr | Compare, Skip if Equal | if (Rd = Rr) PC _ PC + 2 or 3 | None | 1/2/3 |
| CP | Rd, Rr | Compare | Rd - Rr | Z, N,V,C,H | 1 |
| CPC | Rd, Rr | Compare with Carry | Rd - Rr - C | Z, N,V,C,H | 1 |
| CPI | Rd, K | Compare Register with Immediate | Rd - K | Z, N,V,C,H | 1 |
| SBRC | Rr, b | Skip if Bit in Register Cleared | if (Rr(b)=0) PC _ PC + 2 or 3 | None | 1/2/3 |
| SBRS | Rr, b | Skip if Bit in Register is Set | if (Rr(b)=1) PC _ PC + 2 or 3 | None | 1/2/3 |
| SBIC | P, b | Skip if Bit in I/O Register Cleared | if (P(b)=0) PC _ PC + 2 or 3 | None | 1/2/3 |
| SBIS | P, b | Skip if Bit in I/O Register is Set | if (P(b)=1) PC _ PC + 2 or 3 | None | 1/2/3 |
| BRBS | s, k | Branch if Status Flag Set | if (SREG(s) = 1) then PC_PC + k + 1 | None | 1/2 |
| BRBC | s, k | Branch if Status Flag Cleared | if (SREG(s) = 0) then PC_PC + k + 1 | None | 1/2 |
| BREQ | k | Branch if Equal | if (Z = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRNE | k | Branch if Not Equal | if (Z = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRCS | k | Branch if Carry Set | if (C = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRCC | k | Branch if Carry Cleared | if (C = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRSH | k | Branch if Same or Higher | if (C = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRLO | k | Branch if Lower | if (C = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRMI | k | Branch if Minus | if (N = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRPL | k | Branch if Plus | if (N = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRGE | k | Branch if Greater or Equal, Signed | if (N _ V= 0) then PC _ PC + k + 1 | None | 1/2 |
| BRLT | k | Branch if Less Than Zero, Signed | if (N _ V= 1) then PC _ PC + k + 1 | None | 1/2 |
| BRHS | k | Branch if Half Carry Flag Set | if (H = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRHC | k | Branch if Half Carry Flag Cleared | if (H = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRTS | k | Branch if T Flag Set | if (T = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRTC | k | Branch if T Flag Cleared | if (T = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRVS | k | Branch if Overflow Flag is Set | if (V = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRVC | k | Branch if Overflow Flag is Cleared | if (V = 0) then PC _ PC + k + 1 | None | 1/2 |
| BRIE | k | Branch if Interrupt Enabled | if (I = 1) then PC _ PC + k + 1 | None | 1/2 |
| BRID | k | Branch if Interrupt Disabled | if (I = 0) then PC _ PC + k + 1 | None | 1/2 |
| Bit and Bit-test
Instructions |
| SBI | P, b | Set Bit in I/O Register | I/O(P,b) _ 1 | None | 2 |
| CBI | P, b | Clear Bit in I/O Register | I/O(P,b) _ 0 | None | 2 |
| LSL | Rd | Logical Shift Left | Rd(n+1) _ Rd(n), Rd(0) _ 0 | Z,C,N,V | 1 |
| LSR | Rd | Logical Shift Right | Rd(n) _ Rd(n+1), Rd(7) _ 0 | Z,C,N,V | 1 |
| ROL | Rd | Rotate Left Through Carry | Rd(0)_C,Rd(n+1)_ Rd(n),C_Rd(7) | Z,C,N,V | 1 |
| ROR | Rd | Rotate Right Through Carry | Rd(7)_C,Rd(n)_ Rd(n+1),C_Rd(0) | Z,C,N,V | 1 |
| ASR | Rd | Arithmetic Shift Right | Rd(n) _ Rd(n+1), n=0..6 | Z,C,N,V | 1 |
| SWAP | Rd | Swap Nibbles | Rd(3..0)_Rd(7..4),Rd(7..4)_Rd(3..0) | None | 1 |
| BSET | s | Flag Set | SREG(s) _ 1 | SREG(s) | 1 |
| BCLR | s | Flag Clear | SREG(s) _ 0 | SREG(s) | 1 |
| BST | Rr, b | Bit Store from Register to T | T _ Rr(b) | T | 1 |
| BLD | Rd, b | Bit load from T to Register | Rd(b) _ T | None | 1 |
| SEC | — | Set Carry | C _ 1 | C | 1 |
| CLC | — | Clear Carry | C _ 0 | C | 1 |
| SEN | — | Set Negative Flag | N _ 1 | N | 1 |
| CLN | — | Clear Negative Flag | N _ 0 | N | 1 |
| SEZ | — | Set Zero Flag | Z _ 1 | Z | 1 |
| CLZ | — | Clear Zero Flag | Z _ 0 | Z | 1 |
| SEI | — | Global Interrupt Enable | I _ 1 | I | 1 |
| CLI | — | Global Interrupt Disable | I _ 0 | I | 1 |
| SES | — | Set Signed Test Flag | S _ 1 | S | 1 |
| CLS | — | Clear Signed Test Flag | S _ 0 | S | 1 |
| SEV | — | Set Two Complement Overflow. | V _ 1 | V | 1 |
| CLV | — | Clear Two Complement Overflow | V _ 0 | V | 1 |
| SET | — | Set T in SREG | T _ 1 | T | 1 |
| CLT | — | Clear T in SREG | T _ 0 | T | 1 |
| SEH | — | Set Half Carry Flag in SREG | H _ 1 | H | 1 |
| CLH | — | Clear Half Carry Flag in SREG | H _ 0 | H | 1 |
| Data Transfer
Instructions |
| MOV | Rd, Rr | Move Between Registers | Rd _ Rr | None | 1 |
| MOVW | Rd, Rr | Copy Register Word | Rd+1:Rd _ Rr+1:Rr | None | 1 |
| LDI | Rd, K | Load Immediate | Rd _ K | None | 1 |
| LD | Rd, X | Load Indirect | Rd _ (X) | None | 2 |
| LD | Rd, X+ | Load Indirect and Post-Inc. | Rd _ (X), X _ X + 1 | None | 2 |
| LD | Rd, - X | Load Indirect and Pre-Dec. | X _ X - 1, Rd _ (X) | None | 2 |
| LD | Rd, Y | Load Indirect | Rd _ (Y) | None | 2 |
| LD | Rd, Y+ | Load Indirect and Post-Inc. | Rd _ (Y), Y _ Y + 1 | None | 2 |
| LD | Rd, - Y | Load Indirect and Pre-Dec. | Y _ Y - 1, Rd _ (Y) | None | 2 |
| LDD | Rd,Y+q | Load Indirect with Displacement | Rd _ (Y + q) | None | 2 |
| LD | Rd, Z | Load Indirect | Rd _ (Z) | None | 2 |
| LD | Rd, Z+ | Load Indirect and Post-Inc. | Rd _ (Z), Z _ Z+1 | None | 2 |
| LD | Rd, -Z | Load Indirect and Pre-Dec. | Z _ Z - 1, Rd _ (Z) | None | 2 |
| LDD | Rd, Z+q | Load Indirect with Displacement | Rd _ (Z + q) | None | 2 |
| LDS | Rd, k | Load Direct from SRAM | Rd _ (k) | None | 2 |
| ST | X, Rr | Store Indirect | (X) _ Rr | None | 2 |
| ST | X+, Rr | Store Indirect and Post-Inc. | (X) _ Rr, X _ X + 1 | None | 2 |
| ST | - X, Rr | Store Indirect and Pre-Dec. | X _ X - 1, (X) _ Rr | None | 2 |
| ST | Y, Rr | Store Indirect | (Y) _ Rr | None | 2 |
| ST | Y+, Rr | Store Indirect and Post-Inc. | (Y) _ Rr, Y _ Y + 1 | None | 2 |
| ST | - Y, Rr | Store Indirect and Pre-Dec. | Y _ Y - 1, (Y) _ Rr | None | 2 |
| STD | Y+q,Rr | Store Indirect with Displacement | (Y + q) _ Rr | None | 2 |
| ST | Z, Rr | Store Indirect | (Z) _ Rr | None | 2 |
| ST | Z+, Rr | Store Indirect and Post-Inc. | (Z) _ Rr, Z _ Z + 1 | None | 2 |
| ST | -Z, Rr | Store Indirect and Pre-Dec. | Z _ Z - 1, (Z) _ Rr | None | 2 |
| STD | Z+q,Rr | Store Indirect with Displacement | (Z + q) _ Rr | None | 2 |
| STS | k, Rr | Store Direct to SRAM | (k) _ Rr | None | 2 |
| LPM | — | Load Program Memory | R0 _ (Z) | None | 3 |
| LPM | Rd, Z | Load Program Memory | Rd _ (Z) | None | 3 |
| LPM | Rd, Z+ | Load Program Memory and Post-Inc | Rd _ (Z), Z _ Z+1 | None | 3 |
| SPM | — | Store Program Memory | (Z) _ R1:R0 | None | - |
| IN | Rd, P | In Port | Rd _ P | None | 1 |
| OUT | P, Rr | Out Port | P _ Rr | None | 1 |
| PUSH | Rr | Push Register on Stack | STACK _ Rr | None | 2 |
| POP | Rd | Pop Register from Stack | Rd _ STACK | None | 2 |
| MCU Control Instructions |
| NOP | — | No Operation | — | None | 1 |
| SLEEP | — | Sleep | (see specific description for Sleep function) | None | 1 |
| WDR | — | Watchdog Reset | (see specific description for WDR/timer) | None | 1 |
| BREAK | — | Break | For On-chip Debug Only | None | N/A |
