20.3 Client Address Masking

The I2C1MSK register (I2C1MSK) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the Client module to respond, whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2C1MSK is set to ‘0010000000’, the Client module will detect both addresses, ‘0000000000’ and ‘0010000000’.

To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by clearing the STRICT bit (I2CxCONL[11]).

Note: As a result of changes in the I2C protocol, the addresses in Table 20-2 are reserved and will not be Acknowledged in Client mode. This includes any address mask settings that include any of these addresses.
Table 20-1. I2Cx Clock Rates(1,2)
FCYFSCLI2CxBRG Value
DecimalHexadecimal
100 MHz1 MHz4129
100 MHz400 kHz11674
100 MHz100 kHz4911EB
80 MHz1 MHz3220
80 MHz400 kHz925C
80 MHz100 kHz392188
60 MHz1 MHz2418
60 MHz400 kHz6945
60 MHz100 kHz294126
40 MHz1 MHz150F
40 MHz400 kHz452D
40 MHz100 kHz195C3
20 MHz1 MHz77
20 MHz400 kHz2216
20 MHz100 kHz9761
Note:
  1. Based on FCY = FOSC/2; Doze mode and PLL are disabled.
  2. These clock rate values are for guidance only. The actual clock rate can be affected by various 
system-level parameters. The actual clock rate should be measured in its intended application.
Table 20-2. I2Cx Reserved Addresses(1)
Client AddressR/W BitDescription
0000 0000General Call Address(2)
0000 0001Start Byte
0000 001xCbus Address
0000 01xxReserved
0000 1xxxHS Mode Host Code
1111 0xxx10-Bit Client Upper Byte(3)
1111 1xxxReserved
Note:
  1. The address bits listed here will never cause an address match independent of address mask settings.
  2. This address will be Acknowledged only if GCEN = 1.
  3. A match on this address can only occur on the upper byte in 10-Bit Addressing mode.