34.2 AC Characteristics and Timing Parameters

Figure 34-1. Load Conditions for I/O Specifications
Figure 34-2. I/O Timing Requirements
Table 34-19. I/O Timing Requirements
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Max.Units
DO31TIORPort Output Rise Time(1)—10ns
DO32TIOFPort Output Fall Time(1)—10ns
DI35TINPINTx Input Pins High or Low Time20—ns
DI40TRPBI/O and CNx Inputs High or Low Time2—TCY
Note:
  1. This parameter is characterized but not tested in manufacturing.
Figure 34-3. External Clock Timing
Table 34-20. External Clock Timing Requirements
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Sym.CharacteristicMin.Max.UnitsConditions
OS10FINExternal CLKI FrequencyDC64MHzEC
Oscillator Crystal Frequency3.510MHzXT
1032MHzHS
OS30TOSL,

TOSH

External Clock in (OSCI) High or 
Low Time0.45 x OS100.55 x OS10nsEC
OS31TOSR,

TOSF

External Clock in (OSCI) Rise or 
Fall Time(1)—10nsEC
Note:
  1. This parameter is characterized but not tested in manufacturing.
Table 34-21. PLL Clock Timing Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Max.Units
OS50FPLLIPLL Input Frequency Range8(2)64MHz
OS51FPFPPhase Frequency Detector Input Frequency 
(after first divider)8FVCO/16MHz
OS52FVCOVCO Output Frequency4001600MHz
OS53TLOCKLock Time for PLL(1)—250µS
Note:
  1. This parameter is characterized but not tested in manufacturing.
  2. Inclusive of FRC Tolerance Specification F20.
Table 34-22. FRC Oscillator Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicMin.Typ.(3)Max.UnitsConditions
F20AFRCFRC Accuracy @ 8 MHz(1,2)-2.0(4)—2.0%-40°C ≤ TA ≤ -5°C
-1.5—1.5%-5°C ≤ TA ≤ +85°C
-2.0—2.0%+85°C ≤ TA ≤ +125°C
F21TFRCFRC Oscillator Start-up Time(5)——15µS
F22STUNEOSCTUN Step-Size—0.05—%/bit
Note:
  1. To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum.
  2. Frequency is calibrated at +25°C and 3.3V. The TUNx bits can be used to compensate for temperature drift.
  3. Data in the “Typ” column are 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
  4. Due to the effect of aging, this value may drift by an additional -0.5% over the lifetime of the device.
  5. This parameter is characterized but not tested in manufacturing.
Table 34-23. BFRC Oscillator Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Max.Units
F40ABFRCBFRC Accuracy @ 8 MHz-1717%
Table 34-24. Internal LPRC Accuracy
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

CharacteristicMin.Max.UnitsConditions
LPRC @ 32.768 kHz
F21LPRC-25+25%-40°C ≤ TA ≤ 0°C
-10+10%0°C ≤ TA ≤ +85°C
-15+15%+85°C ≤ TA ≤ +125°C
Figure 34-4. BOR and Master Clear Reset Timing Characteristics
Table 34-25. Reset, Watchdog Timer, Oscillator Start-up Timer Timing Requirements
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SY00TPUPower-up Period—200—µsFNOSC[2:0] are FRC
SY10TOSTOscillator Start-up—1024 TOSC——TOSC = OSCI period
SY13TIOZI/O High-Impedance from MCLR

Low or Watchdog Timer Reset

—1.5—µs
SY20TMCLRMCLR Pulse Width (low)2——µs
SY30TBORBOR Pulse Width (low)1——µs
SY35TFSCMFail-Safe Clock Monitor Delay——40µs
SY37TOSCDFRCFRC Oscillator Start-up Delay——15µsFrom POR event
SY38TOSCDLPRCLPRC Oscillator Start-up Delay——50µsFrom Reset event
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in the “Typ.” column are at 3.3V, +25°C unless otherwise stated.
Figure 34-5. High-Speed PWMx Module Timing Characteristics
Table 34-26. High-Speed PWMx Module Timing Requirements
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymbolCharacteristic(1)Min.Max.Units
MP10FINPWM Input Frequency—500MHz
MP20TFDFault Input ↓ to PWMx I/O Change—26ns
MP30TFHFault Input Pulse Width8—ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
Figure 34-6. SPIx Host Mode (Half-Duplex, Transmit Only, CKE = 0) 
Timing Characteristics
Figure 34-7. SPIx Host Mode (Half-Duplex, Transmit Only, CKE = 1) 
Timing Characteristics
Table 34-27. SPIx Host Mode (Half-Duplex, Transmit Only) Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time———nsSee Parameter DO31

(Note 3)

SP21TSCRSCKx Output Rise Time———nsSee Parameter DO31

(Note 3)

SP30TDOFSDOx Data Output Fall Time———nsSee Parameter D032

(Note 3)

SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31

(Note 3)

SP35TSCH2DOV,
TSCL2DOVSDOx Data Output Valid After SCKx Edge—620ns
SP36TDIV2SCH,
TDIV2SCLSDOx Data Output Setup to First SCKx Edge30——nsUsing PPS pins
3——nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 34-8. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) 
Timing Characteristics
Table 34-28. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = X, SMP = 1) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time———nsSee Parameter D032 (Note 3)
SP21TSCRSCKx Output Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter D032 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After SCKx Edge—620ns
SP36TDOV2SC, TDOV2SCLSDOx Data Output Setup to First SCKx Edge30——nsUsing PPS pins
3——nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input to SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 34-9. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) 
Timing Characteristics
Table 34-29. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time———nsSee Parameter D032 (Note 3)
SP21TSCRSCKx Output Rise Time———nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter D032 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After SCKx Edge—620ns
SP36TDOV2SCH, TDOV2SCLSDOx Data Output Setup to
First SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP40TdiV2SCH, TdiV2SCLSetup Time of SDIx Data Input to SCKx Edge30——nsUsing PPS pins
10——nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 34-10. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) 
Timing Characteristics
Table 34-30. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolChar.(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Input Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP72TSCFSCKx Input Fall Time—6.17.5ns
SP73TSCRSCKx Input Rise Time—6.17.5ns
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After
 SCKx Edge—620ns
SP36TDOV2SCH, TDOV2SCLSDOx Data Output Setup to
 First SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
10——nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
SP50TSSL2SCH, TSSL2SCLSSx ↓ to SCKx ↑ or SCKx ↓ Input120——ns
SP51TSSH2DOZSSx ↑ to SDOx Output
High-Impedance8—50ns(Note 3)
SP52TSCH2SSH,

TSCL2SSH

SSx ↑ After SCKx Edge1.5 TCY + 40——ns(Note 3)
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 34-11. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) 
Timing Characteristics
Table 34-31. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) 
Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(1)Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Input 
Frequency——15MHzUsing PPS pins
——40MHzSPI2 dedicated pins
SP72TSCFSCKx Input Fall Time—6.17.5nsSee Parameter DO32 (Note 3)
SP73TSCRSCKx Input Rise Time—6.17.5nsSee Parameter DO31 (Note 3)
SP30TDOFSDOx Data Output Fall Time———nsSee Parameter DO32 (Note 3)
SP31TDORSDOx Data Output Rise Time———nsSee Parameter DO31 (Note 3)
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After
 SCKx Edge—620ns
SP36TDOV2scH, TDOV2SCLSDOx Data Output Setup to
 First SCKx Edge30——nsUsing PPS pins
20——nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
10——nsSPI2 dedicated pins
SP41TSCH2diL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge30——nsUsing PPS pins
15——nsSPI2 dedicated pins
SP50TSSL2SCH, TssL2scLSSx ↓ to SCKx ↑ or SCKx ↓ Input120——ns
SP51TSSH2doZSSx ↑ to SDOx Output
High-Impedance8—50ns(Note 3)
SP52TSCH2SSH,

TSCL2SSH

SSx ↑ After SCKx Edge1.5 TCY + 40——ns(Note 3)
SP60TSSL2DOVSDOx Data Output Valid After SSx Edge——50ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 50 pF load on all SPIx pins.
Figure 34-12. I2Cx Bus Start/Stop Bits Timing Characteristics (Host Mode)
Figure 34-13. I2Cx Bus Data Timing Characteristics (Host Mode)
Table 34-32. I2Cx Bus Data Timing Requirements (Host Mode)
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicsMin.(1)Max.UnitsConditions
IM10TLO:SCLClock Low Time100 kHz modeTCY * (BRG + 1)—µs
400 kHz modeTCY * (BRG + 1)—µs
1 MHz modeTCY * (BRG + 1)—µs
IM11THI:SCLClock High Time100 kHz modeTCY * (BRG + 1)—µs
400 kHz modeTCY * (BRG + 1)—µs
1 MHz modeTCY * (BRG + 1)—µs
IM20TF:SCLSDAx and SCLx
Fall Time100 kHz mode—300ns
400 kHz mode20 x (VDD/5.5V)300ns
1 MHz mode20 x (VDD/5.5V)120ns
IM21TR:SCLSDAx and SCLx
Rise Time100 kHz mode—1000ns
400 kHz mode20 + 0.1 Cb300ns
1 MHz mode—120ns
IM25TSU:DATData Input
Setup Time100 kHz mode250—ns
400 kHz mode100—ns
1 MHz mode50—ns
IM26THD:DATData Input
Hold Time100 kHz mode03.45µs
400 kHz mode00.9µs
1 MHz mode00.3µs
IM30TSU:STAStart Condition
Setup Time100 kHz modeTCY * (BRG + 1)—µsOnly relevant for Repeated Start condition
400 kHz modeTCY * (BRG + 1)—µs
1 MHz modeTCY * (BRG + 1)—µs
IM31THD:STAStart Condition Hold Time100 kHz modeTCY * (BRG + 1)—µsAfter this period, the first clock pulse is generated
400 kHz modeTCY * (BRG + 1)—µs
1 MHz modeTCY * (BRG + 1)—µs
IM33TSU:STOStop Condition Setup Time100 kHz modeTCY * (BRG + 1)—µs
400 kHz modeTCY * (BRG + 1)—µs
1 MHz modeTCY * (BRG + 1)—µs
IM34THD:STOStop Condition

Hold Time

100 kHz modeTCY * (BRG + 1)—ns
400 kHz modeTCY * (BRG + 1)—ns
1 MHz modeTCY * (BRG + 1)—ns
IM40TAA:SCLOutput Valid from Clock100 kHz mode—3450ns
400 kHz mode—900ns
1 MHz mode—450ns
IM45TBF:SDABus Free Time100 kHz mode4.7—µsThe amount of time the bus must be free before a new
transmission can start
400 kHz mode1.3—µs
1 MHz mode0.5—µs
IM50CBBus Capacitive Loading100 kHz mode—400pF
400 kHz mode—400pF
1 MHz mode—10pF
IM51TPGDPulse Gobbler Delay65390ns
Note:
  1. BRG is the value of the I2C Baud Rate Generator.
Figure 34-14. I2Cx Bus Start/Stop Bits Timing Characteristics (Client Mode)
Figure 34-15.  I2Cx Bus Data Timing Characteristics (Client Mode)
Table 34-33. I2Cx Bus Data Timing Requirements (Client Mode)
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param
 No.Sym.CharacteristicsMin.Max.UnitsConditions
IS10TLO:SCLClock Low Time100 kHz mode4.7—µsCPU clock must be minimum

800 kHz

400 kHz mode1.3—µsCPU clock must be minimum

3.2 MHz

1 MHz mode0.5—µs
IS11THI:SCLClock High Time100 kHz mode4.0—µsCPU clock must be minimum

800 kHz

400 kHz mode0.6—µsCPU clock must be minimum

3.2 MHz

1 MHz mode0.26—µs
IS20TF:SCLSDAx and SCLx

Fall Time

100 kHz mode—300ns
400 kHz mode20 x (VDD/5.5V)300ns
1 MHz mode20 x (VDD/5.5V)120ns
IS21TR:SCLSDAx and SCLx Rise Time100 kHz mode—1000ns
400 kHz mode20 + 0.1 Cb300ns
1 MHz mode—120ns
IS25TSU:DATData Input
Setup Time100 kHz mode250—ns
400 kHz mode100—ns
1 MHz mode50—ns
IS26THD:DATData Input
Hold Time100 kHz mode03.45ns
400 kHz mode00.9µs
1 MHz mode00.3µs
IS30TSU:STAStart Condition
Setup Time100 kHz mode4.7—µsOnly relevant for Repeated

Start 
condition

400 kHz mode0.6—µs
1 MHz mode0.26—µs
IS31THD:STAStart Condition 
Hold Time100 kHz mode4.0—µsAfter this period, the first clock pulse is generated
400 kHz mode0.6—µs
1 MHz mode0.26—µs
IS33TSU:STOStop Condition Setup Time100 kHz mode4.0—µs
400 kHz mode0.6—µs
1 MHz mode0.26—µs
IS34THD:STOStop Condition

Hold Time

100 kHz mode> 0—µs
400 kHz mode> 0—µs
1 MHz mode> 0—µs
IS40TAA:SCLOutput Valid from Clock100 kHz mode03.45µs
400 kHz mode00.9µs
1 MHz mode00.45µs
IS45TBF:SDABus Free Time100 kHz mode4.7—µsThe amount of time the bus must be free before a new transmission can start
400 kHz mode1.3—µs
1 MHz mode0.5—µs
IS50CBBus Capacitive Loading100 kHz mode—400pF
400 kHz mode—400pF
1 MHz mode—10pF
Figure 34-16. UARTx Module Timing Characteristics
Table 34-34. UARTx Module Timing Requirements
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(1)Min.Max.Units
UA10TUABAUDUARTx Baud Time40—ns
UA11FBAUDUARTx Baud Rate—40Mbps
UA20TCWFStart Bit Pulse Width to Trigger UARTx Wake-up50—ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
Figure 34-17. QEI Module Index Pulse Timing Characteristics
Table 34-35. QEI Index Pulse Timing Requirements

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Sym.Characteristic(1)Min.Max.UnitsConditions
TQ50TqIL

Filter Time to Recognize Low with Digital Filter

3 * N * TCY—ns

N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2)

TQ51TqiH

Filter Time to Recognize High with Digital Filter

3 * N * TCY—ns

N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2)

TQ52Tqidxr

Index Pulse Recognized to Position Counter Reset (ungated index)

3 TCY—ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). The same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on the falling edge.
Table 34-36. ADC Module Specifications
Operating Conditions (unless otherwise stated):(4)

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicsMin.Typ.(1)Max.UnitsConditions
Input
AD9FSRCADC Module Input Frequency——500MHzClock frequency selected by the CLKSELx bits
AD10FCORESRCADC Control Clock Frequency——250MHzClock frequency after the first divider controlled by the CLKDIVx bits
AD11FADCOREADC SAR Core Clock Frequency——70MHzSAR core frequency after the second divider controlled by the ADCSx or SHRADCSx bits
AD12VINH-VINLFull-Scale Input SpanAVSS—AVDDV
AD14VINAbsolute Input VoltageAVSS – 0.3—AVDD + 0.3V
AD17RINRecommended Impedance of Analog Voltage Source—100—ΩFor minimum sampling time
AD61CHOLDCapacitance—12.5—pF
AD62RICInput Resistance(1)—5001000Ω
AD66VBGInternal Band Gap Input Voltage1.141.21.26V
ADC Accuracy
AD20NrResolution12 data bitsbits
AD21bINL_1SIntegral Nonlinearity-3-1.5/+1.5+3LSb

3.5 Msps (5),

TADC = 4nS (250 MHz),

TCORESRC = 8 nS (125 MHz),

TADCORE = 16 nS (62.5 MHz),

Sampling Time = 4 TADCORE,

VDD = 3.3V, AVDD = 3.3V

AD22bDNL_1SDifferential Nonlinearity-1-1/+1.5+3LSb
AD23bGERR_1SGain Error—+4—LSb
AD24bOERR_1SOffset Error—-4—LSb
AD21dINL _3S

Integral Nonlinearity

—-5/+5—LSb

2.7 Msps(6),

TADC = 4 nS (250 MHz),

TCORESRC = 8 nS (125 MHz),

TADCORE = 16 nS (62.5 MHz),

Sampling Time = 10 TADCORE,

VDD = 3.3V, AVDD = 3.3V,

all core conversions are started simultaneously.

AD22dDNL_3S

Differential Nonlinearity

—-1/+2—LSb
AD23dGERR_3S

Gain Error

—+5—LSb
AD24dOERR_3S

Offset Error

—-5—LSb
AD25c—Monotonicity———LSbGuaranteed
Dynamic Performance
AD31bSINADSignal-to-Noise and 
Distortion56—70dBNotes 2,3
AD34bENOBEffective Number of Bits9.810.211.4bitsNotes 2,3
AD50TADADC Clock Period14.3——ns
AD51FTPThroughput Rate——2.7MspsShared Core (Note 5)
Note:
  1. These parameters for design guidance only and are not characterized or tested in manufacturing.
  2. These parameters are characterized but not tested in manufacturing.
  3. Characterized with a 1 kHz sine wave.
  4. The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is ensured, but not characterized.
  5. The throughput includes 10 TADCORE sampling time and 13 TADCORE conversion time.
Table 34-37. Die Temperature Diode Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicMin.Typ.Max.UnitsConditions
TD01TCOEFFTemperature Coefficient—-1.5—mV/CNote 1
Note:
  1. These parameters are for design guidance only and are not characterized or tested in manufacturing.
Table 34-38. High-Speed Analog Comparator Module Specifications
Operating Conditions (unless otherwise stated):(2)

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param No.Sym.CharacteristicMin.Typ.(1)Max.UnitsComments
CM09FINInput Frequency400—500MHz-40°C ≤ TA ≤ +85°C
400—480+85°C < TA ≤ +125°C
CM10VIOFFInput Offset Voltage-20—20mV
CM11VICMInput Common-Mode Voltage RangeAVSS—AVDDVNote 1
CM13CMRRCommon-Mode Rejection Ratio65——dBNote 1
CM14TRESPLarge Signal Response—15—nsV+ input step of 100 mV while V- input is held at AVDD/2
CM15VHYSTInput Hysteresis15—45mVDepends on HYSSEL[1:0](1)
Note:
  1. These parameters are for design guidance only and are not tested in manufacturing.
  2. The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested but not characterized.
Table 34-39. DACx Module Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsComments
DA02CVRESResolution12bits
DA03INLIntegral Nonlinearity Error-38—0LSB
DA04DNLDifferential Nonlinearity Error-5—5LSB
DA05EOFFOffset Error-3.5—21.5LSB
DA06EGGain Error0—41LSB
DA07TSETSettling Time6007502000nsOutput with 2% of desired output voltage with a 10-90% or 90-10% Step
DA08VOUTVoltage Output Range0.165—3.135VVDD = 3.3V
DA09TTRTransition Time—340—ns
DA10TSSSteady-State Time—550—ns
Note:
  1. Data in the “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing.
Table 34-40. DAC Output (DACOUT1 Pin) Specifications(1,2)
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Sym.CharacteristicMin.Typ.Max.UnitsComments
DA11RLOADResistive Output Load Impedance10k——Ohm
DA11aCLOADOutput Load Capacitance——35pFIncluding output pin capacitance
DA12IOUTOutput Current Drive Strength—3—mASink and source
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
  2. The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
Table 34-41. Current Bias Generator Specifications(1)
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicMin.Max.Units
CC03I10SRC10 µA Source Current8.811.2µA
CC04I50SRC50 µA Source Current4456µA
CC05I50SNK50 µA Sink Current-44-56µA
Note:
  1. Parameters are characterized but not tested in manufacturing.
Table 34-42. Operational Amplifier Specifications
Operating Conditions (unless otherwise stated):

3.0V ≤ VDD ≤ 3.6V, 
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Sym.CharacteristicMin.Typ.(1)Max.UnitsComments
OA01GBWPGain Bandwidth Product—20—MHz
OA02SRSlew Rate—24—V/µs
OA03VIOFFInput Offset Voltage-3(3)-1/+1+3(3)mVUnity gain configuration
-8-3/+3+8mVOpen-loop configuration
OA04VIBCInput Bias Current———nANote 2
OA05VICM

Common-Mode Input Voltage Range

AVSS—AVDDVNCHDISx = 0
AVSS—AVDD – 1.4VNCHDISx = 1
OA07CMRRCommon-Mode Rejection Ratio—68—dB
OA08PSRRPower Supply Rejection Ratio—74—dB
OA09VOROutput Voltage RangeAVSS—AVDDmV

0.5V input overdrive, no output loading (Note 1)

OA11CLOADOutput Load Capacitance——30uF

Including output pin capacitance (Note 1)

OA12IOUTOutput Current Drive Strength—3—mASink and source
OA13PMARGINPhase Margin44——degreeUnity gain (Note 1)
OA14GMARGINGain Margin7——dBUnity gain (Note 1)
OA15OLGOpen-Loop Gain6875—Note 1
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
  2. The op amps use CMOS input circuitry with negligible input bias current. The maximum “effective bias current” is the I/O pin leakage specified by electrical Parameter DI50.
  3. This parameter is characterized but not tested in manufacturing.