4.1 PIC32CZ CA90 Curiosity Ultra Development Board

To develop and run the application, follow these steps:

  1. Click Projects and then under Source files open the main.c file of the project and add the required variables outside the main() function.
    uint8_t __attribute__ ((aligned(32))) Tx[10] = {0x1F, 0x2F, 0x3F, 0x4F, 0x5F, 0x6F, 0x7F, 0x8F, 0x9F, 0xAF};
    uint8_t __attribute__ ((aligned(32)))Rx[10];
    
    /* transfer done flag */
    volatile bool Rx_transfer_done = false;
    volatile bool Tx_transfer_done = false;
    
  2. Add the DMA Event Handler for both Tx and Rx outside the main() function.
    /* This is called after transfer is done */
    void Tx_DMA_EventHandler(DMA_TRANSFER_EVENT event, uintptr_t context)
    {
        if (event == DMA_TRANSFER_EVENT_BLOCK_TRANSFER_COMPLETE)
        {
            Tx_transfer_done = true;
        }
    }
    
    void Rx_DMA_EventHandler(DMA_TRANSFER_EVENT event, uintptr_t context)
    {
        if (event == DMA_TRANSFER_EVENT_BLOCK_TRANSFER_COMPLETE)
        {
            Rx_transfer_done = true;
        }
    }
    
    Figure 4-1. Adding Macros, Variables, and Event Handlers
  3. Add the DMA Callback register function, cache invalidate function, and DMA Channel transfer function.
    DMA_ChannelCallbackRegister(DMA_CHANNEL_0, Tx_DMA_EventHandler, (uintptr_t)NULL);
        DMA_ChannelCallbackRegister(DMA_CHANNEL_1, Rx_DMA_EventHandler, (uintptr_t)NULL);
        
        DCACHE_INVALIDATE_BY_ADDR((uint32_t *)Tx, 10);
        DCACHE_INVALIDATE_BY_ADDR((uint32_t *)Rx, 10);
        
        DMA_ChannelTransfer(DMA_CHANNEL_1, (void *)&SERCOM2_REGS->SPIM.SERCOM_DATA, Rx, sizeof(Rx));
        DMA_ChannelTransfer(DMA_CHANNEL_0, Tx, (void *)&SERCOM2_REGS->SPIM.SERCOM_DATA, sizeof(Tx));
    
    Note: Cache invalidation is crucial for maintaining data consistency and accuracy, especially in dynamic systems where data frequently changes. By invalidating the cache, it ensures that the next time the data is requested, it will be fetched from the original source rather than the cache.
    Figure 4-2. Application Logic