5.2 Decoding
SPI cmd Sequence without FEC | Comment |
---|---|
Set System mode (0x22, 0x40, 0x00) | Receive data |
— | — |
Read Rx FIFO (3, 0x00, data0, data1, data2) | Read received data from FIFO |
SPI Cmd Sequence with FEC | Comment |
---|---|
Set System mode (0x22, 0x40, 0x00) | Receive data |
Write SRAM/Register (1, 0x04, 0x00, 0x01) | Start decryption (FECCR.SD) of FIFO data |
Read SRAM/Register (3, 0x04, 0x02, 0x00, data0, data1, data2) | Read decrypted data from FECRXDB buffer |