Introduction
The dsPIC33CDVL256MC506 family devices that you have received confirm functionally to the current device data sheet (DS70005628B), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
The errata described in this document will be addressed in future revisions of dsPIC33CDVL256MC506 family silicon.
Data sheet clarifications and corrections start on Data Sheet Clarifications, following the discussion of silicon issues.
The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are available at the Microchip corporate website (www.microchip.com).
To determine the silicon revision level using MPLAB IDE with a hardware debugger, follow these steps:
- Connect the device to the hardware debugger using the appropriate interface.
- Open an MPLAB IDE project.
- Configure the MPLAB IDE project for the correct device and hardware debugger.
- From MPLAB X IDE, navigate to Window >
Dashboard, and then click the Refresh Debug
Tool Status icon (
). - The part number and Device Revision ID value appear in the Output window,
depending on the development tool used. Note: If you cannot retrieve the silicon revision level, contact your local Microchip sales office for support.
The following table lists the DEVREV values for the various silicon revisions of the dsPIC33CDVL256MC506 family.
| Part Number | Device ID (1) | Revision ID for Silicon Revision (1) |
|---|---|---|
| D3 | ||
| dsPIC33CDVL256MC506 | 0xA27A | 0x0003 |
| dsPIC33CDVL128MC506 | 0xA26A | |
| dsPIC33CDV256MC506 | 0xA25A | |
| dsPIC33CDV128MC506 | 0xA24A | |
| dsPIC33CDVL256MC106 | 0xA23A | |
| dsPIC33CDVL128MC106 | 0xA22A | |
| dsPIC33CDV256MC106 | 0xA21A | |
| dsPIC33CDV128MC106 | 0xA20A | |
|
Note:
| ||
| Module | Feature | Item Number | Issue Summary | Affected Revisions |
|---|---|---|---|---|
| D3 | ||||
| ADC | Differential-Mode | 1 | Errors may occur when enabling Differential-mode when FSRC > 50 MHz. | X |
| CCP | CCP | 2 |
The timer interrupt is not working in Capture mode. | X |
| CPU | DIV.SD
Instruction | 3 |
The Overflow bit is not set when an overflow occurs. | X |
| I2C | Idle | 4 | The address cannot be received in Idle mode. | X |
| PWM | Time Base Capture | 5 | The PWM Capture Status (CAP) flag will not set again under certain conditions. | X |
| MOSFET Gate Driver | XUVLO Fault Detection | 6 | An erroneous XUVLO fault may be triggered after any device Reset when the high-side driver is enabled for the first time. | X |
