6. Module: MOSFET Gate Driver

An erroneous XUVLO (External MOSFET Under Voltage Lockout) fault may be triggered after any device Reset when the high-side driver is enabled for the first time. This will disable the HSx outputs. This issue affects only the XUVLO fault on high-side gate drivers.

Clear the XUVLO upon initiating high-side gate driver sequence using one of the following work around options. After the work around sequence, read the STAT0 and STAT1 registers to ensure the fault has been cleared successfully. Once the initial fault is cleared, the device will resume normal operation.

#define OE LATCbits.LATC13
#define FAULT PORTDbits.RD1
while(!FAULT){
OE = 0; 			     //disable OE
__delay_us(400); 		//400uS delay to avoid device entering standby mode after OE is put low
OE = 1; 			     //enable OE
}

Work Around #2

1. Monitor the FAULT signal until active.
2. Disable the Output Enable (OE) pin.
3. Send new configuration data to the CFG0 via DE2 communication pin.
4. Enable the OE pin.

Work Around #2 Code Sequence

//initialize UART module for DE2 communication. Refer to MOSFET Gate Driver device chapter
describing DE2 communication port
#define OE LATCbits.LATC13
#define FAULT PORTDbits.RD1
while(!FAULT){
OE = 0; 				           //disable OE
U1TXREG = 0x81; 			       //send first byte,write to CFG0 register of MOSFET gate driver
while(U1STAHbits.URXBE == 1);      //wait for transmission to complete
U1TXREG = 0x07; 			       //configure MOSFET Gate Driver with XUVLO enabled
while(U1STAHbits.URXBE == 1);      //wait for transmission to complete
OE = 1; 					       //enable OE
}