1. Module: ADC
When using the ADC in Differential-mode (DIFFx = 1) with an input
frequency (FSRC) above 50 MHz, the first result data may be
incorrect. The Single-Ended Channel mode is unaffected by this
errata. | |||||||||||||||||
| Work around Use a slower input frequency of 50 MHz or less during ADC initialization to write to ADMODxL/H registers. After completion of the first data conversion for each channel in Differential-mode, the input frequency (FSRC) can be increased to the maximum specified frequency in the “Electrical Characteristics” section of the device data sheet. | |||||||||||||||||
Affected Silicon Revisions
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