9 Getting Started with TCB

The capabilities of the 16-bit Timer/Counter type B (TCB) include frequency, waveform generation, and input capture on an event with time and frequency measurement of the digital signals. The TCB consists of a base counter and a control logic that can be set in one of the eight different modes, each mode providing unique functionality. The base counter is clocked by the peripheral clock with optional prescaling, as shown below.

Use case description: TCB (the TCB3 instance) will be configured in 8-bit PWM mode and generate a one second period PWM signal, at a 50% duty cycle. A GPIO pin (Port B pin 5 - PB5) will be used as an output to showcase the signal.

Result: TCB will generate a 50% duty cycle PWM signal with a period of one second. The on-board LED (the PB5 pin) will toggle every 500 ms.

This timer can be configured to run in 8-bit PWM mode where each of the register pairs in the 16-bit Capture/Compare register (TCBn.CCMPH and TCBn.CCMPL) is used as an individual Compare register. The counter will continuously count from zero to CCMPL and the output will be set at BOTTOM and cleared when the counter reaches CCMPH.

PORTB_DIR |= PIN5_bm;
PORTB_OUT |= PIN5_bm;

The Main Clock and Prescaler Configuration (CLKCTRL.MCLKCTRLA, CLKCTRL.MCLKCTRLB) registers are protected by the Configuration Change Protection (CCP) mechanism, employing a timed-write procedure for changing these registers. To write to these registers, a certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four CPU instructions.

Since the desired frequency is the lowest possible, the Prescaler (PEN) must be enabled and PDIV must be set to ‘64’ divider.

The key that must be written to the CPU.CPP register is IOREG. For more details, check the Configuration Change Protection (CCP) section in the megaAVR 0-series family data sheet.

Writing to a protected register is done by using the ccp_write_io function, which translates into the line of code from below for enabling the ‘64’ prescaler divider.

ccp_write_io((void *) &(CLKCTRL.MCLKCTRLB), (CLKCTRL_PDIV_64X_gc | CLKCTRL_PEN_bm));

OSCULP32K must be selected, which means the CLKSEL bit field must be set to the value 0x1. This translates into the following code.

ccp_write_io((void *) &(CLKCTRL.MCLKCTRLA) , (CLKCTRL_CLKSEL_OSCULP32K_gc));

The clock switching process is indicated by the SOSC bit. The program must halt during an undergoing switch of the clock source, so a wait until the switch is over will be implemented:

while (CLKCTRL.MCLKSTATUS & CLKCTRL_SOSC_bm)
{
    ;
}

When running TCB in 8-bit PWM mode, TCBn.CCMPL must be loaded with the PWM signal period, of one second in this case. Since the period of the output pulse is defined by TCBn.CCMPL+1, the value that must be loaded into the TCBn.CCMPL register is 0xFF (255 in decimal).

Subsequently, TCBn.CCMPH must be loaded with the number of cycles for which the output will be driven high. The goal is to set the duty cycle at 50% to make PB5 toggle every 500 ms.

This means that TCBn.CCMP must be loaded with the following value, obtained from TCBn.CCMPH and TCBn.CCMPL:

TCB3.CCMP = 0x80FF;

TCB3 can be enabled by setting the ENABLE bit to ‘1’ in the TCB3.CTRLA register. This translates into the following code.

TCB3.CTRLA |= TCB_ENABLE_bm;

To get the lowest possible frequency, CLK_PER will be further divided by 2, by configuring the CLKSEL bit field in the TCB3.CTRLA register. The corresponding value for CLKSEL, in this case, is 0x1. This translates into the following code.

TCB3.CTRLA |= TCB_CLKSEL_CLKDIV2_gc;

CCMPEN must be enabled. This translates into the following code.

TCB3.CTRLB |= TCB_CCMPEN_bm;

TCB must be configured for the 8-bit PWM mode. This translates into the following code.

TCB3.CTRLB |= TCB_CNTMODE_PWM8_gc;

An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here:

Use case description: Configure TCB in Time-Out Check mode and measure the signal time generated by a GPIO (configured as an input). The time-out will be set to one second and the event system will be used to detect the rising and falling edges of the signal generated by a GPIO (e.g., a push button in a real application). If the time-out expires, another GPIO (e.g., an LED in a real application) will be toggled in the interrupt.

Result: Use a GPIO as input to generate an event that serves as the input signal for TCB. Generate an interrupt when the time-out expires.

In the Time-Out Check mode, TCB relies on the interaction with the event system, as displayed in the figure below. In this mode, the counter counts to MAX and wraps around. On the first edge, the counter is restarted. On the second edge, the counter is stopped. If the Count (TCBn.CNT) register reaches TOP before the second edge, an interrupt will be generated. In the Freeze state, the counter will restart on a new edge. Reading count (TCBn.CNT) or the Capture/Compare (TCBn.CCMP) register, or writing the RUN bit (RUN in TCBn.STATUS) in Freeze state will have no effect.

1. TCB0.CCMP Configuration

   The TCB Capture/Compare register must be loaded with the value of the time-out. For this document, a value of one second for the time-out has been chosen. With an input frequency of 32.768 kHz, the 16-bit counter will make a complete cycle in two seconds (the maximum value of a 16-bit number is 65535).

   The reload value of TCB0.CCMP can be calculated, as shown below:

   $$\begin{gathered} CCMP=\frac{CNT\max }{2} \\ CCMP=\frac{65535}{2} \\ CCMP=32767.5 \end{gathered}$$

   A value of 32767.5 cannot be translated into hex, so 32767 will be used instead.

   $CCMP=32767.5=\sim 32767=0\times 7FFF$

   The following code snippet will load TCB0.CCMP with 0x7FFF time-out value.

   TCB0.CCMP = 0x7fff;

2. TCBn.INTCTRL Configuration

   TCB0.CNT will start increasing as soon as a signal edge is detected on the event system bus. If the complementary edge of the signal is not detected within the time-out, TCB0 will trigger an interrupt. In this regard, capture or time-out interrupt must be enabled in the TCB0.INCTRL register. The following code snippet enables the interrupt.

   TCB0.INTCTRL = TCB_CAPT_bm;

   Note: The global interrupts must also be enabled. This can be done at a later step in the software program.
3. TCBn.EVCTRL Configuration

   The target is to measure the signal time between the falling edge and the rising edge of the PB2 input pin (in Idle, the pin is kept in high state). This means both CAPTEI and EDGE bits must be set to ‘1’. The following code snippet enables both bits in the TCB0.EVCTRL register.

   TCB0.EVCTRL = TCB_CAPTEI_bm | TCB_EDGE_bm;

4. EVSYS.CHANNEL Configuration

   Each channel can be connected to a one-event generator. Not all generators can be connected to all channels. Refer to the table below to see which generator sources can be routed onto each channel and the generator value that must be written to EVSYS.CHANNELn to achieve this routing. The value 0x00 in EVSYS.CHANNELn turns the channel off.

   EVSYS.CHANNEL must be loaded with the value 0x4A for PB2 to generate an input event, as represented in the following code snippet.

   EVSYS.CHANNEL0 = EVSYS_GENERATOR_PORT1_PIN2_gc;

5. EVSYS.USER Configuration

   Each event user can be connected to one channel. Several users can be connected to the same channel. The following table lists all event system users, with their corresponding user ID number. This ID number corresponds to the USER register index, e.g., the user with ID 2 is controlled by the EVSYS.USER2 register.

   The user channel must be linked to the event channel already configured previously (in EVSYS.CHANNEL). The following code snippet illustrates how this can be done.

   EVSYS.USERTCB0 = EVSYS_CHANNEL_CHANNEL0_gc;

An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here:

Use case description: Configure TCB to generate an overflow interrupt every second, even when the microcontroller is in Standby sleep mode, and toggle a GPIO pin (PB5).

Result: TCB overflow interrupt will be triggered every one second, regardless of the running mode of the microcontroller (Idle/Standby). In the Interrupt Service Routine (ISR), the on-board LED, corresponding to PB5, will be toggled.

TCBn is by default disabled in Standby sleep mode; as soon as the microcontroller enters sleep mode, TCB will be halted. The module can stay fully operational in Standby sleep mode if the Run In Standby (RUNSTDBY) bit in the TCBn.CTRLA register is written to ‘1’.

SLPCTRL.CTRLA = SLPCTRL_SMODE_gm | SLPCTRL_SMODE_STDBY_gc;

TCB0.CCMP = 0x7fff; 

TCB0.CTRLA = TCB_CLKSEL_CLKDIV1_gc | TCB_ENABLE_bm | TCB_RUNSTDBY_bm;

TCB0.INTCTRL = TCB_CAPT_bm;

PORTB_DIR |= PIN5_bm;
PORTB_OUT |= PIN5_bm;

An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here: