4 Pin Configuration

VDD2/INH

1

1

70 mA, 3.3V supply voltage/INH is the high-voltage output designed to control an external voltage regulator.

LH

2

2

Limp Home – High-voltage failure output, Open drain

VS

3

3

Battery supply pin

WAKE

4

4

High-voltage input for local wake-up

GNDLIN

5

—

LIN transceiver ground

LIN

6

—

LIN bus interface

GND

7

5

LDO and analog ground

SL

8

—

Low-side MOSFET source terminal, in 40 pin package internally connected to PGND

VG

9

6

12V gate drive regulator/charge pump 1 output

GL1

10

7

Gate driver output for low-side MOSFET, phase 1

GL2

11

8

Gate driver output for low-side MOSFET, phase 2

GL3

12

9

Gate driver output for low-side MOSFET, phase 3

CPP1

13

10

Charge pump 1 flying capacitor positive connection 1

CPN1

14

11

Charge pump 1 flying capacitor negative connection 1

VDH

15

12

Supply for VG and charge pump, high-side drain-source voltage monitoring reference, reference voltage level for charge pump 2 reservoir capacitor

CPN2

16

13

Charge pump 2 flying capacitor negative connection 2

CPP2

17

14

Charge pump 2 flying capacitor positive connection 2

VCP

18

15

Charge pump 2 reservoir capacitor, gate drive supply of high-side MOSFET gate drivers

SH1

19

16

Motor connection terminal 1 and phase 1 high-side MOSFET source terminal

GH1

20

17

Gate driver output for high-side MOSFET, phase 1

SH2

21

18

Motor connection terminal 2 and phase 2 high-side MOSFET source terminal

GH2

22

19

Gate driver output for high-side MOSFET, phase 2

SH3

23

20

Motor connection terminal 3 and phase 3 high-side MOSFET source terminal

GH3

24

21

Gate driver output for the high-side MOSFET, phase 3

OPN3

25

22

Current sense OpAmp 3 inverting input

OPP3

26

23

Current sense OpAmp 3 non-inverting input

OPO3

27

24

Current sense OpAmp 3 output

OPN2

28

—

Current sense OpAmp 2 inverting input

OPP2

29

—

Current sense OpAmp 2 non-inverting input

OPO2

30

—

Current sense OpAmp 2 output

OPN1/BEMF1

31

25

Current sense OpAmp 1 inverting input/Back-EMF feedback phase 1

OPP1/BEMF2

32

26

Current sense OpAmp 1 non-inverting input/Back-EMF feedback phase 2

OPO1/BEMF3

33

27

Current sense OpAmp 1 output/Back-EMF feedback phase 3

NRES

34

28

Input/output pin for resetting microcontroller, pull-up to VIO, active low

IL1

35

29

Low-side digital driver input – use in direct control mode to activate GL1 or in complementary control mode as enable line for phase 1

NIH1

36

30

High-side digital driver input – use in direct control mode to activate GH1 or in complementary control mode as PWM input for phase 1, active low

IL2

37

31

Low-side digital driver input – use in direct control mode to activate GL2 or in complementary control mode as enable line for phase 2

NIH2

38

32

High-side digital driver input – use in direct control mode to activate GH2 or in complementary control mode as PWM input for phase 2, active low

IL3

39

33

Low-side digital driver input – use in direct control mode to activate GL3 or in complementary control mode as enable line for phase 3

NIH3

40

34

High-side digital driver input – use in direct control mode to activate GH3 or in complementary control mode as PWM input for phase 3, active low

NIRQ

41

35

Interrupt output, pull-up to VIO, active low

RXD

42

—

Receive data output from LIN transceiver

TXD

43

—

Transmit data input into LIN transceiver

NCS

44

36

SPI chip-select, active low

SDO

45

37

SPI Serial Data Output

SDI

46

38

SPI Serial Data Input

SCK

47

39

SPI Clock Input

VDD1

48

40

100 mA, 5V/3.3V supply voltage

PGND

EP

EP

Exposed Thermal Pad: Heat slug, general device ground