38.4.4 I/O Pins

Table 38-7. I/O Pin Specifications^{(1)
(5)}
Symbol	Description	Min.	Typ.✝	Max.	Units	Conditions
Input Low Voltage
V_IL	I/O PORT:
With Schmitt Trigger buffer	—	—	0.2 × V_DD	V	PINnCTRL.INLVL = `0x00`
TTL level	—	—	0.8	V	PINnCTRL.INLVL = `0x01` V_DD > 2.7V
TWI PORT:
With I²C levels	—	—	0.3 × V_DD	V	CTRLA.INPUTLVL = `0x0`
With SMBus 3.0 levels			0.8	V	CTRLA.INPUTLVL = `0x1`
RESET Pin	—	—	0.2 × V_DD	V
Input High Voltage
V_IH	I/O PORT:
With Schmitt Trigger buffer	0.8 × V_DD	—	—	V	PINnCTRL.INLVL = `0x00`
TTL level	2.0	—	—	V	PINnCTRL.INLVL = `0x01` V_DD > 2.7V
TWI PORT:
With I²C levels	0.7 × V_DD	—	—	V	CTRLA.INPUTLVL = `0x0`
With SMBus 3.0 levels	1.35	—	—	V	CTRLA.INPUTLVL = `0x1` 0°C ≤ T_A ≤ +125°C, 2.5V ≤ V_DD ≤ 5.5V
1.45	—	—	V	CTRLA.INPUTLVL = `0x1` 0°C ≤ T_A ≤ +125°C, 1.8V ≤ V_DD ≤ 5.5V
RESET Pin	0.8 × V_DD	—	—	V
Input Leakage Current⁽²⁾
I_IL	I/O PORTS⁽³⁾	—	±5	±125	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A= 85°C
—	±5	±1000	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A = 125°C
RESET Pin⁽⁴⁾ *	—	±50	±200	nA	GND ≤ V_PIN ≤ V_DD, pin at high-impedance, T_A= 85°C
Pull-up Current
I_PUR		90	150	200	μA	V_DD = 3.0V, V_PIN = GND
Output Low Voltage
V_OL	Standard I/O Ports	—	—	0.6	V	I_OL = 10 mA, V_DD = 3.0V
Output High Voltage
V_OH	Standard I/O Ports	V_DD - 0.7	—	—	V	I_OH = 6 mA, V_DD = 3.0V
I/O Slew Rate
	Rising slew rate	—	22	—	ns	PORTCTRL.SRL = `0x00`
Rising slew rate	—	45	—	ns	PORTCTRL.SRL = `0x01`
Falling slew rate	—	30	—	ns	PORTCTRL.SRL = `0x01`
Falling slew rate	—	16	—	ns	PORTCTRL.SRL = `0x00`
Pin Capacitance
C_IO	V_REFpin	—	7	—	pF
XTAL pins	—	4	—	pF
Other pins	—	4	—	pF
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. * These parameters are characterized but not tested in production. Note: These figures are valid for all I/O ports regardless of if they are connected to the V_DD or V_DDIO2 power domain. The negative current is the current sourced by the pin. The leakage current numbers for I/O PORTS are also valid when the pin is used as input to an enabled analog peripheral. The leakage current on the RESET pin strongly depends on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages. The input voltage threshold is relative to VDDIO2 on MVIO pins (PORTC) and VDD on other pins.

Input Low Voltage

V_IL

I/O PORT:

With Schmitt Trigger buffer

—

0.2 × V_DD

V

PINnCTRL.INLVL = 0x00

TTL level

—

0.8

V

PINnCTRL.INLVL = 0x01

V_DD > 2.7V

TWI PORT:

With I²C levels

—

0.3 × V_DD

V

CTRLA.INPUTLVL = 0x0

With SMBus 3.0 levels

0.8

V

CTRLA.INPUTLVL = 0x1

RESET Pin

—

0.2 × V_DD

V

Input High Voltage

V_IH

I/O PORT:

With Schmitt Trigger buffer

0.8 × V_DD

—

V

PINnCTRL.INLVL = 0x00

TTL level

2.0

—

V

PINnCTRL.INLVL = 0x01

V_DD > 2.7V

TWI PORT:

With I²C levels

0.7 × V_DD

—

V

CTRLA.INPUTLVL = 0x0

With SMBus 3.0 levels

1.35

—

V

CTRLA.INPUTLVL = 0x1

0°C ≤ T_A ≤ +125°C,

2.5V ≤ V_DD ≤ 5.5V

1.45

—

V

CTRLA.INPUTLVL = 0x1

0°C ≤ T_A ≤ +125°C,

1.8V ≤ V_DD ≤ 5.5V

RESET Pin

0.8 × V_DD

—

V

Input Leakage Current⁽²⁾

I_IL

I/O PORTS⁽³⁾

—

±5

±125

nA

GND ≤ V_PIN ≤ V_DD,

pin at high-impedance, T_A= 85°C

—

±5

±1000

nA

GND ≤ V_PIN ≤ V_DD,

pin at high-impedance, T_A = 125°C

RESET Pin⁽⁴⁾ *

—

±50

±200

nA

GND ≤ V_PIN ≤ V_DD,

pin at high-impedance, T_A= 85°C

Pull-up Current

I_PUR

90

150

200

μA

V_DD = 3.0V, V_PIN = GND

Output Low Voltage

V_OL

Standard I/O Ports

—

0.6

V

I_OL = 10 mA, V_DD = 3.0V

Output High Voltage

V_OH

Standard I/O Ports

V_DD - 0.7

—

V

I_OH = 6 mA, V_DD = 3.0V

I/O Slew Rate

Rising slew rate

—

22

—

ns

PORTCTRL.SRL = 0x00

Rising slew rate

—

45

—

ns

PORTCTRL.SRL = 0x01

Falling slew rate

—

30

—

ns

PORTCTRL.SRL = 0x01

Falling slew rate

—

16

—

ns

PORTCTRL.SRL = 0x00

Pin Capacitance

C_IO

V_REFpin

—

7

—

pF

XTAL pins

—

4

—

pF

Other pins

—

4

—

pF

✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.

Note:

These figures are valid for all I/O ports regardless of if they are connected to the V_DD or V_DDIO2 power domain.
The negative current is the current sourced by the pin.
The leakage current numbers for I/O PORTS are also valid when the pin is used as input to an enabled analog peripheral.
The leakage current on the RESET pin strongly depends on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.
The input voltage threshold is relative to VDDIO2 on MVIO pins (PORTC) and VDD on other pins.

AVR64DD14/20

38.4.4 I/O Pins