6.5.2 Statistics Registers
The statistics register block is located within Memory Map Selector 1 (MMS1) beginning with the Statistics 0 Register at 0x288 and runs through to the Statistics 11 Register at 0x293. The statistic registers consist of the statistic counters listed in Table 6-3 below.
| Receive Symbol Errors | Multicast Hash Match Frames Received |
| Length Field Errors | Broadcast Frames Received |
| Oversize Frames Received | VLAN Tagged Frames Received |
| Undersize Frames Received | Total Frames Received |
| Receive Resource Errors | Frames Received Without Error |
| Receive Buffer Overrun Errors | Transmit Abort Internal Errors |
| Receive FIFO Overrun Errors | Transmit Abort External Errors |
| Multiple Start-of-Packet Errors | Transmit FIFO Underrun Errors |
| Frame Check Sequence Errors | Transmit Buffer Underrun Errors |
| Type ID Match Frames Received | Excessive Collisions |
| Specific Address Match Frames Received | Total Frames Transmitted |
| Unicast Hash Match Frames Received | Frames Transmitted Without Error |
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of statistics data.
The receive statistics registers are only incremented when the receive enable bit (RXEN) is set in the Network Control (MAC_NCR) register.
Once a statistics register has been read, it is automatically cleared.