Data Sheet Revision History
| Revision Level & Date | Section/Figure/Entry | Correction |
|---|---|---|
| DS60001734F (Aug-2025) | Section 3.3 Pin Descriptions | Added behavior of pins while in reset |
| Section 3.4 Configurable DIO Pins |
Clarified default behavior Updated relationship links | |
| Section 4.1 Reset and Startup | Corrected links to other sections | |
| Section 4.1.1.3 Software Reset | Corrected relevant registers and bitfields | |
| Section 4.1.2 Startup Sequence | Corrected relevant registers and bitfields | |
| Section 4.4.4 Wake-up | Corrected bit indicating wake-up | |
| Section 4.6.1.4/7.2.5 | Moved section 4.6.1.4 Transmit Collisions to Chapter/Section 7.2.5 | |
| Section 9.1 | Remove reference to IBEE CAN EMC ratings | |
| Table 9-9 | Correcting SPI Timing | |
| Register 11.2.19 TSU Timer Increment Sub-nanoseconds Register | Corrected description of LSBTIR bitfield | |
| Register 11.5.50 Sleep Control 1 Register | Removed bits 3 and 4, which were erroneously included | |
| DS60001734E (Jan-2024) | Figure 2-1 | Correcting duplicate MAC TX to MAC RX |
| Tables 3-3, 3-5 | Clarifying which power supply pull-ups should connect to | |
| Figure 4-7 | Replacing with correct diagram | |
| 4.5.4.2 | Correcting DIOMUX register reference to PADCTRL | |
| Figure 8-5 | Fix typo in power sequencing diodes, 1.8Vsw | |
| Table 9-2 | Add footnote limiting junction temperature to 135°C | |
| 11.5 | Added SQI Configuration 2 (SQICFG2) register | |
| 11.6.52 | Correcting Phase Adjuster Error from bit 30 to 29 | |
| DS60001734D (Aug-2023) | All | Update for silicon revision 2 (product revision B1) |
| DS60001734C (Feb-2023) | Table 9.4 | Updated Power Consumption for LAN8651. |
| DS60001734B (Feb-2023) | All | Update for silicon revision 1 (product revision B0) |
| DS60001734A (Nov-2021) | All | Initial for silicon revision 0 (product revision A0) |