11 Register Descriptions

The OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification defines the register memory map selector (MMS) field as a 4 bit field which allows for up to 16 different memory maps. The standard further defines which MMS should be used for required registers and register classes in a compliant device, including mapping of registers required by the 10BASE‑T1S standard. The standard also includes areas for vendor specific information.

This chapter describes the device registers of the LAN8650/1, organized by MMS value.

Table 11-1. Control and Status Register Memory Map Selector (MMS)
MMS	Width (bits)	Description of Registers
0	32/16	Open Alliance 10BASE-T1x MAC-PHY Standard Registers including PHY Clause 22 Basic Control and Status Registers
1	32	MAC Registers
2	16	PHY PCS Registers
3	16	PHY PMA/PMD Registers
4	16	PHY Vendor Specific Registers
5-9	-	Reserved
10	16	Miscellaneous Register Descriptions
11-15	-	Reserved

For details on register bit attribute notation, refer to the section Register Bit Types.