5.3.1 Control Command Header

All control and status register data reads/writes are performed with Control Transactions. All Control transactions, regardless of read or write, are preceded by a 32‑bit Control Command Header as shown in the following table:

Table 5-4. Control Command Header Format
Bit	31	30	29	28	27	26	25	24
	DNC=0	HDRB	WNR	AID	MMS

Bit	23	22	21	20	19	18	17	16
	ADDR[15:8]

Bit	15	14	13	12	11	10	9	8
	ADDR[7:0]

Bit	7	6	5	4	3	2	1	0
	LEN							P

Bit 31 - DNC

Data, Not Control - Flag indicating the type of transaction, data or control.


0	Control (register read/write)
1	Data (Ethernet frame)

Note: The DNC bit is always zero to indicate a control command and distinguish it from a frame data block header.

Bit 30 - HDRB

Header Bad - Indication from the LAN8650/1 to the SPI host that the MAC-PHY received a transaction header with an invalid parity. When sent to the LAN8650/1 by the SPI host, the value of this bit is ignored by the LAN8650/1.

Bit 29 - WNR

Write, Not Read - This bit indicates the type of control access to perform.


0	Control/Status register read
1	Control/Status register write

Bit 28 - AID

Address Increment Disable - Normally, when this bit is 0, the address is post-incremented by one following each read/write register access within the same control command. When this bit is 1, subsequent reads or writes within the same control command will result in the same register address being accessed. This feature is useful for reading and writing register FIFOs located at a single address.


0	Register address will automatically be post-incremented following each read/write within the same control command.
1	Register address will not be post-incremented following each read/write within the same control command, allowing successive access to the same register address.

Bits 27:24 - MMS

Memory Map Selector - This bit field selects the LAN8650/1 memory map to be accessed

Bits 23:8 - ADDR

Address - This field specifies the address of the first register to access within the selected memory map.

Bits 7:1 - LEN

Length - This field specifies the number of successive registers to read/write within the control command. The length is the number of registers to access minus one. Up to 128 consecutive registers may be read or written by a single control command. When accessing only a single register, this field is zero.

Bit 0 - P

Parity - Parity bit over bits 31:1 of the control command header field. This field is set such that there is an odd total number of bits set within the header.

Note: The parity bit will be updated by the LAN8650/1 if it is echoed back to the SPI host with the Header Bad (HDRB) bit set.