Description

The LAN8650/1 combines a Media Access Controller (MAC) and an Ethernet PHY to enable low‑cost microcontrollers, including those without an on-board MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface (SPI) of the LAN8650/1 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8650/1 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.

Ethernet packets are segmented and transferred over the serial interface according to the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification. The serial interface protocol can simultaneously transfer both transmit and receive packets between the station controller and the LAN8650/1, using either store and forward or cut-through packet handling.

Highlights

  • High-performance 10BASE‑T1S single-pair Ethernet PHY designed to IEEE Std. 802.3cg™-2019
    • 10 Mbit/s over a single balanced pair
      • Half-duplex multidrop mixing segments up to at least 25m with up to at least 8 PHYs
      • Half-duplex point-to-point link segments up to at least 15m
  • Physical Layer Collision Avoidance (PLCA)
    • Burst mode for transmission of multiple packets for latency-sensitive applications
    • Minimize latency for time-sensitive applications by assigning multiple PLCA IDs per node
  • Carrier Sense Multiple Access / Collision Detection (CSMA/CD) media access control
  • Application Controlled Media Access (ACMA) for implementation of collision-free Time-Division Multiple Access (TDMA) methods
  • Integrated Media Access Controller (MAC)
  • Industry standard Serial Peripheral Interface (SPI), designed to the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification, V1.1
  • Support for Time Sensitive Networks (IEEE Std 802.1AS™ / IEEE 1588™)
    • Internal wall clock
    • Event generation and event capture synchronized to the wall clock
    • Phase adjuster for the wall clock to minimize microcontroller overhead
    • Packet timestamping
  • Credit-based traffic shaping

  • EtherGREEN™ Energy Efficiency

    • Ultra-low power sleep mode
    • Wake up triggered by either MDI activity or local WAKE_IN
    • WAKE_OUT pulse assertion; INH output for enable/disable of ECU supply
  • Over-temperature and under-voltage protection
  • Cable fault diagnostics and Signal Quality Indication (SQI) support

  • Enhanced electromagnetic compatibility / electromagnetic interference (EMC/EMI) performance

  • Single 3.3V supply with integrated 1.8V regulator (LAN8651)
  • Small footprint 32-pin (5 x 5 mm) VQFN package with wettable flanks
  • -40°C to +125°C extended temperature range
  • AEC-Q100 qualification
  • Functional Safety Support: Functional Safety Manual, FMEDA, Dependent Failure Analysis (DFA)

Target Applications

  • In-vehicle networking and automotive zonal architecture
  • Sensor/actuator networks and machine control
  • Industrial control cabinets and building automation
  • LED lighting

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