Parameters
(Ask a Question)The following table lists the Two-Port Large SRAM parameters in the generated macro.
| Parameter | Valid Range | Default (Condition) | Description |
|---|---|---|---|
| LPMTYPE | LPM_RAM | LPM_RAM | Macro category. |
| PTYPE | 1, 2 | 1 |
1: Two-port. 2: Dual-port. |
| INIT_RAM | F, T | F |
F: No RAM initialization for simulation. T: Initialize RAM for simulation. |
| IMPORT_FILE | — |
IMPORT_FILE Dummy parameter (INIT_RAM=T) |
Memory file to be imported to initialize RAM. No Tcl support yet |
| CASCADE | 0, 1 | 0 |
0: Cascading for WIDTH or Speed. 1: Cascading for DEPTH or Power. |
| CLKS | 1, 2 | 1 |
1: Single Read/Write clock. 2: Independent Read and Write clocks. |
| CLOCK_PN |
CLK CLK_N |
CLK (CLKS=1) | Single clock Port name. |
| CLK_EDGE | RISE, FALL |
RISE (CLKS=1) |
RISE: Rising edge Single clock. FALL: Falling edge Single clock. |
| WCLOCK_PN |
WCLK WCLK_N |
WCLK (CLKS=2) | Write clock Port name |
| RCLOCK_PN |
RCLK RCLK_N |
RCLK (CLKS=2) | Read clock Port name. |
| WCLK_EDGE | RISE, FALL |
RISE (CLKS=2) |
RISE: Rising edge Write clock. FALL: Falling edge Write clock. |
| RCLK_EDGE | RISE, FALL |
RISE (CLKS=2) |
RISE: Rising edge Read clock. FALL: Falling edge Read clock. |
| WWIDTH | 1-7524 | 18 | Write data width. |
| WDEPTH | 1-65536 | 1024 | Write address depth. |
| RWIDTH | 1-7524 | 18 | Read data output width. |
| RDEPTH | 1- 65536 | 1024 | Read address depth. |
| WE_POLARITY | 0, 1, 2 | 1 |
0: Active-low W_EN_N port will be exposed to exercise Write port enable. 1: Active-high W_EN port will be exposed to exercise Write port enable. 2: Write port enable tied off to be always active. |
| WE_PN |
WEN WEN_N |
WEN
| Write port enable Port name. |
| RE_POLARITY | 0, 1, 2 | 2 |
0: Active-low R_EN_N port will be exposed to exercise Read port enable. 1: Active-high R_EN port will be exposed to exercise Read port enable. 2: Read port enable tied off to be always active. |
| RE_PN |
REN REN_N |
REN
| Read port enable Port name. |
| RPMODE | 0, 1 | 0 |
0: Bypass Read data register. 1: Pipeline Read data. |
| DATA_OUT_PN | — | RD | Read data Port name. |
| A_DOUT_EN_POLARITY | 0, 1, 2 |
2 (RPMODE =1) |
0: Active-low A_DOUT_EN_N port will be exposed to exercise Port A read data register enable. 1: Active-high A_DOUT_EN port will be exposed to exercise Port A read data register enable. 2: Port A read data register enable tied off to be always active. |
| A_DOUT_EN_PN |
RD_EN RD_EN_N |
RD_EN (RPMODE =1) | Read data register enable Port name. |
| A_DOUT_SRST_POLARITY | 0, 1, 2 |
2 (RPMODE =1) |
0: Active-low A_DOUT_SRST_N port will be exposed to exercise Port A read data register Sync-reset 1: Active-high A_DOUT_SRST port will be exposed to exercise Port A read data register Sync-reset 2: Port A read data register Sync- reset tied off to be always inactive. |
| A_DOUT_SRST_PN |
RD_SRST RD_SRST_N
|
RD_SRST_N (RPMODE =1) |
Read data register Sync-reset Port name. |
| ARST_N_POLARITY | 0, 1, 2 |
2 (RPMODE =1) |
Asynchronous Reset Polarity 0: Active-low ARST_N port will be exposed to exercise Read data register Async reset 1: Active-high ARST port will be exposed to exercise Read data register Async reset 2: Read data register Async-reset tied off to be always inactive |
| RESET_PN |
ARST_N ARST |
ARST_N (RPMODE =1) | Read data register Async-reset Port name. |
| ECC | 0, 1, 2 | 0 |
0: ECC disabled. 1: ECC Pipelined. 2: ECC Non-pipelined. |
| DATA_IN_PN | — | WD | Write data Port name. |
| WADDRESS_PN | — | WADDR | Write address Port name. |
| RADDRESS_PN | — | RADDR | Read address Port name. |
| BYTEENABLES | 0, 1 | 0 |
0: Do not generate WBYTE_EN. 1: Generate WBYTE_EN. |
| A_WBYTE_EN_PN | — | WBYTE_EN | Write Byte enable port name |
| BYTE_ENABLE_WIDTH | — | 0 |
Write port Byte Enable width Values are based on the configuration |