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RTG4 Two-Port Large SRAM Configuration User Guide RTG4™
Introduction
Using the RTG4 Two-Port Large SRAM
Optimization for High Speed or Low Power
Write Depth/Width and Read Depth/Width
Single Clock (CLK) or Independent Write and Read Clocks (WCLK, RCLK)
Write Enable (WEN)
Read Enable (REN)
Pipeline for Read Data Output
Register Enable (RD_EN)
Synchronous Reset (RD_SRST_N)
Asynchronous Reset (ARST_N)
Expose Write Byte Enables (WBYTE_EN)
Error Correction Code (ECC)
RD Register Truth Table
Internal Configurator Connections
WEN Connections
REN Connections
WD Connections
RD Logic
SB_CORRECT and DB_DETECT Logic
Caveats for Two-Port Large SRAM Generation
Supported Formats
1 Intel HEX
2 Motorola S-Record
3 Write Port Width Alignment
RAM Content Manager
Opening and Using RAM Content Manager
1 MEMFILE (RAM Content Manager Output File)
Port Description
Parameters
1 Revision History
Microchip FPGA Support
Microchip Information
The Microchip Website
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Customer Support
Microchip Devices Code Protection Feature
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