2.3 Advanced Configuration

For advanced use cases, the following flow is recommended to configure the clock generated by the selected CCC:

1. Select the number of desired output clocks (up to four).
2. Set the required output frequency, for each selected output clock. Output frequency cannot be set when the selected output clock has an input from a clock generated by Clock Recovery Circuitry.
3. Select the desired reference clock input from which the output is derived, for each selected output clock. It can be:
   • One of CCC input clocks (PLL bypass mode), which can be one of four Dedicated Pads or one of four FPGA Fabric Inputs
   • One of eight PLL output phases
   • 50 MHz Oscillator
   • One of two Clock Recovery Circuits
4. If required:
   • Select the PLL reference clock source and frequency
   • Select the PLL feedback source
5. Enter the frequency of each selected source clock(s) either as the PLL reference or direct source for the output. The configurator uses those frequencies to compute the division factor of the PLL reference and feedback dividers as well as the GPD dividers.

The configurator automatically tries to compute a configuration that meets the frequency requirements and all the internal CCC/PLL constraints. If the configurator is unable to find an exact solution for all requirements, it finds a configuration that globally minimizes the error between the required and actual frequency.

Actual data (divider settings, PLL output frequency, and actual outputs frequencies) are shown in the Advanced tab in blue.