Signal integrity issues on CA or DQ lines. When the Write Leveling training fails, a dialog box
appears as shown in the following figure.Figure 5-3. Write Leveling
Training Fail
Workaround
Configure any one of the following parameters to a different value using the MSS Configurator when the Write Leveling training fails:
FPGA ADD/CMD Drive
FPGA Vref data (as % of
bank vddi)
The following figure shows the configuration of ADD/CMD drive or Vref data
in the DDR Controller tab.Figure 5-4. Configuring ADD/CMD
Drive or Vref Data—DDR Controller Tab
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
