25.6.4 Slave Receiver Mode
In the Slave Receiver (SR) mode, a number of data bytes are received from a Master Transmitter (see figure below). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows:
The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.TWGCI=1, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
TWCR must hold a value of the type TWCR=0100010x - TWCR.TWEN must be written to '1' to enable the TWI. TWCR.TWEA bit must be written to '1' to enable the acknowledgement of the device’s own slave address or the general call address. TWCR.TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address, if enabled) followed by the data direction bit. If the direction bit is '0' (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action, as detailed in the table below. The SR mode may also be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78).
If the TWCR.TWEA bit is reset during a transfer, the TWI will return a "Not Acknowledge" ('1') to SDA after the next received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by writing '1' to it). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
| Status Code (TWSR) Prescaler Bits are 0 | Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware | Application Software Response | Next Action Taken by TWI Hardware | ||||
|---|---|---|---|---|---|---|---|
| To/from TWDR | To TWCR | ||||||
| STA | STO | TWINT | TWEA | ||||
| 0x60 | Own SLA+W has
been received; ACK has been returned | No TWDR action
or No TWDR action | X X | 0 0 | 1 1 | 0 1 | Data byte will
be received and NOT ACK will be returned Data byte will be received and ACK will be returned |
| 0x68 | Arbitration
lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned | No TWDR action
or No TWDR action | X X | 0 0 | 1 1 | 0 1 | Data byte will
be received and NOT ACK will be returned Data byte will be received and ACK will be returned |
| 0x70 | General call
address has been received; ACK has been returned | No TWDR action
or No TWDR action | X X | 0 0 | 1 1 | 0 1 | Data byte will
be received and NOT ACK will be returned Data byte will be received and ACK will be returned |
| 0x78 | Arbitration lost in SLA+R/W as Master; General call address has been received; ACK has been returned | No TWDR action
or No TWDR action | X X | 0 0 | 1 1 | 0 1 | Data byte will
be received and NOT ACK will be returned Data byte will be received and ACK will be returned |
| 0x80 | Previously addressed with own SLA+W; data has been received; ACK has been returned | Read data byte
or Read data byte | X X | 0 0 | 1 1 | 0 1 | Data byte will
be received and NOT ACK will be returned Data byte will be received and ACK will be returned |
| 0x88 | Previously addressed with own SLA+W; data has been received; NOT ACK has been returned | Read data byte
or Read data byte or Read data byte or Read data byte | 0 0 1 1 | 0 0 0 0 | 1 1 1 1 | 0 1 0 1 | Switched to
the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free |
| 0x90 | Previously
addressed with general call; data has been received; ACK has been returned | Read data byte
or Read data byte | X X | 0 0 | 1 1 | 0 1 | Data byte will
be received and NOT ACK will be returned Data byte will be received and ACK will be returned |
| 0x98 | Previously
addressed with general call; data has been received; NOT ACK has been returned | Read data byte
or Read data byte or Read data byte or Read data byte | 0 0 1 1 | 0 0 0 0 | 1 1 1 1 | 0 1 0 1 | Switched to
the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free |
| 0xA0 | A STOP
condition or repeated START condition has been received while still addressed as Slave | No action | 0 0 1 1 | 0 0 0 0 | 1 1 1 1 | 0 1 0 1 | Switched to
the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free |
