19.6 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T₀) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. The following figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value.

Figure 19-3. Timer/Counter Timing Diagram, No Prescaling

The next figure shows the same timing data, but with the prescaler enabled.

Figure 19-4. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

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