23.5.1 SPCR – SPI Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
| Name: | SPCR |
| Offset: | 0x0D |
| Reset: | 0x00 |
| Property: | When addressing I/O Registers as data space the offset address is 0x2D |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPIE | SPE | DORD | MSTR | CPOL | CPHA | SPRn[1:0] | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – SPIE SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set.
Bit 6 – SPE SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
Bit 5 – DORD Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 – MSTR Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode.
Bit 3 – CPOL Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to the figures in Data Modes for an example. The CPOL functionality is summarized below:
| CPOL | Leading Edge | Trailing Edge |
|---|---|---|
| 0 | Rising | Falling |
| 1 | Falling | Rising |
Bit 2 – CPHA Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to the figures in Data Modes for an example. The CPHA functionality is summarized below:
| CPHA | Leading Edge | Trailing Edge |
|---|---|---|
| 0 | Sample | Setup |
| 1 | Setup | Sample |
Bits 1:0 – SPRn[1:0] SPI Clock Rate Select [n = 1:0]
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below.
| SPI2X | SPR1 | SPR0 | SCK Frequency |
|---|---|---|---|
| 0 | 0 | 0 | fosc/4 |
| 0 | 0 | 1 | fosc/16 |
| 0 | 1 | 0 | fosc/64 |
| 0 | 1 | 1 | fosc/128 |
| 1 | 0 | 0 | fosc/2 |
| 1 | 0 | 1 | fosc/8 |
| 1 | 1 | 0 | fosc/32 |
| 1 | 1 | 1 | fosc/64 |