30.5.3 Control C
| Name: | CTRLC |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMPCAP | REFSEL[1:0] | PRESC[2:0] | |||||||
| Access | R | R/W | R/W | R/W | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 6 – SAMPCAP Sample Capacitance Selection
| Value | Description |
|---|---|
| 0 | Recommended for reference voltage values below 1V. |
| 1 | Reduced size of sampling capacitance. Recommended for higher reference voltages. |
Bits 5:4 – REFSEL[1:0] Reference Selection
These bits select the voltage reference for the ADC.
Note: Do not force the internal
reference enabled (ADCnREFEN=1 in VREF.CTRLB) when the ADC is using the
external reference (REFSEL bits in ADC.CTRLC).
| Value | Name | Description |
|---|---|---|
| 0x0 | INTERNAL | Internal reference |
| 0x1 | VDD | VDD |
| 0x2 | VREFA | External reference VREFA |
| Other | - | Reserved. |
Bits 2:0 – PRESC[2:0] Prescaler
These bits define the division factor from the peripheral clock (CLK_PER) to the ADC clock (CLK_ADC).
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV2 | CLK_PER divided by 2 |
| 0x1 | DIV4 | CLK_PER divided by 4 |
| 0x2 | DIV8 | CLK_PER divided by 8 |
| 0x3 | DIV16 | CLK_PER divided by 16 |
| 0x4 | DIV32 | CLK_PER divided by 32 |
| 0x5 | DIV64 | CLK_PER divided by 64 |
| 0x6 | DIV128 | CLK_PER divided by 128 |
| 0x7 | DIV256 | CLK_PER divided by 256 |