2.3.3 Clocks

CPUPLLCK, comprising the L2 cache controller and L2 cache memory, feeds the Cortex-A7 processor, the L1 cache, the Neon MPE, the ETM and the GIC.

CPUPLLCK is divided (MCK0) to feed the rest of the core subsystem and the CSS AXI matrix.

The L2 cache controller runs at CPU frequency. The L2 cache memories run at one half of the CPU clock frequency.

The CPU frequency can be adapted to the application requirements with frequency and voltage scaling, including power saving, in case high performance is not required. Refer to VDDCPU characteristics in the section "Electrical Characteristics" for more details.

To optimize performance, a path dedicated to high frequency exists between the CPU and UDDRC. It is clocked by MCK4. Refer to the section "System Interconnect and Security (SIS)" for more details.