2.3.2 Embedded Characteristics

The Cortex-A7 processor (r0p5) implements the Arm v7-A architecture. This includes:

32-bit Arm Instruction Set
Thumb Instruction Set featuring 16-bit and 32-bit Instructions
ThumbEE Instruction Set
Implementation of the Jazelle Extension
Arm v7 Debug Architecture
TrustZone Security Extensions
Harvard Level 1 Memory System with a Memory Management Unit (MMU)
32 Kbytes L1 Data Cache
32 Kbytes L1 Instruction Cache
256 Kbytes L2 Cache
Generic Interrupt Controller (GIC)
Media Processing Engine (MPE) with Neon Technology
Trace Support through an Embedded Trace Macrocell (ETM) Interface
Performance Monitoring Unit (PMU)

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