3.4.3.2.1 Initialization

The initialization sequence has two phases. The first phase happens automatically at reset and is as follows:

  1. Before and during configuration reset, the DDR3PHY is un-initialized and remains in this state until the reset is de-asserted.
  2. At reset de-assertion, the DDR3PHY moves into the DLL initialization (lock) phase. This phase may be bypassed at any time by writing a '1' to the DLL initialization bypass register bit (DDR3PHY_PIR.LOCKBYP).
  3. In parallel to DLL initialization, the impedance calibration phase also starts at reset de-assertion. This phase can also be bypassed by writing a '1' to the impedance calibration bypass register bit (DDR3PHY_PIR.ZCALBYP).
  4. If the DDR3PHY initialization sequence was triggered by the user, a soft reset may optionally be selected to be issued to the ITMs. Initialization that is automatically triggered on reset does not issue a soft reset to the ITMs because the components have already been reset by the main reset.
  5. Once the DLL initialization and impedance calibration phases are done and after the ITMs are reset, the DDR3PHY is initialized. Note that if these phases were bypassed, it is up to the user to perform them using software, or to trigger them at a later time before the DDR3PHY can be used.

The following figure shows a high-level illustration of the DDR3PHY initialization sequence.

Figure 3-53. DDR3PHY Initialization Flow

The above figure shows the timing diagram for the first phase of DDR3PHY initialization which happens automatically after reset is de-asserted.

The DLL soft reset and ITM soft reset are executed only when the first phase is triggered by the user through the Initialization register (DDR3PHY_PIR).

The second initialization phase starts after the DDR3PHY is initialized. Each step of this phase is triggered by the user or memory controller:

  1. The user or memory controller performs SDRAM initialization sequence. The DRAM mode registers and necessary timing parameters must first be programmed before triggering SDRAM initialization.
  2. After the SDRAM is initialized, the user or memory controller performs DDR_DQS gate training (“Built-in DDR_DQS Gate Training”). The SDRAM must be initialized before triggering DDR_DQS gate training.
  3. The user or memory controller performs read data valid training.
  4. The user or memory controller performs read data eye training.
  5. The DDR3PHY is now ready for SDRAM read/write accesses.