6.3.6.3 Supported Modes

LVDSC supports the following modes:

  • 24-bit, Single Channel, DC-Unbalanced
  • 18-bit, Single Channel, DC-Unbalanced
  • 24-bit, Single Channel, DC-Balanced
  • 18-bit, Single Channel, DC-Balanced
Figure 6-32. VESA Format, 24-bit, Single Channel, DC-Unbalanced
Figure 6-33. VESA Format, 18-bit, Single Channel, DC-Unbalanced

The following figures illustrate balanced operating modes. In addition to pixel and control information, an additional bit, DCBAL, is transmitted on every signal line during each cycle. DCBAL bit minimizes the short- and long-term DC bias on the signal lines. The LVDSC sends the pixel data either unmodified or inverted. The value of the DCBAL bit is 0 when the data is sent unmodified and 1 when the data is sent inverted.

Figure 6-34. 24-bit, Single Channel, DC-Balanced
Figure 6-35. 18-bit, Single Channel, DC-Balanced