7.7.6.2 ASRC Mode Register
This register can only be written if the WPEN bit is cleared in ASRC_WPMR.
| Name: | ASRC_MR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DARHR3 | DARHR2 | DARHR1 | DARHR0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DATHR3 | DATHR2 | DATHR1 | DATHR0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DARHRM | DATHRM | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ASRCEN3 | ASRCEN2 | ASRCEN1 | ASRCEN0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 24, 25, 26, 27 – DARHRx Direct Access Receive Holding Register Destination
| Value | Name | Description |
|---|---|---|
| 0 | DMA |
The Receive Holding register is read by software or DMA. If DARHRM=1, the Receive Holding register is directly driving an audio peripheral. The Receive Holding register x loads the audio peripheral selected by ASRC_DAPSELR.OUT_CHx. |
| 1 | DIRECT_ACCESS |
The Receive Holding register is directly driving an audio peripheral. The Receive Holding register x loads the audio peripheral selected by ASRC_DAPSELR.OUT_CHx. |
Bits 16, 17, 18, 19 – DATHRx Direct Access Transmit Holding Register Source
| Value | Name | Description |
|---|---|---|
| 0 | DMA |
The Transmit Holding register is loaded by software or DMA. If DATHRM=1, the Transmit Holding register is directly loaded by an audio peripheral. The audio peripheral loading the Transmit Holding Register is selected by configuring ASRC_DAPSELR.IN_CHx. |
| 1 | DIRECT_ACCESS |
The Transmit Holding register is directly loaded by an audio peripheral. The audio peripheral loading the Transmit Holding Register is selected by configuring ASRC_DAPSELR.IN_CHx. |
Bit 9 – DARHRM Direct Access Receive Holding Registers Mode
| Value | Name | Description |
|---|---|---|
| 0 | PER_RHR | The access mode for each receive channel (ASRC_RHRx) is defined by the DARHRx bits. |
| 1 | ALL_RHR | All receive channels are directly driving audio peripherals. The DARHRx bits have no effect. |
Bit 8 – DATHRM Direct Access Transmit Holding Registers Mode
| Value | Name | Description |
|---|---|---|
| 0 | PER_THR | The access mode for each transmit channel (ASRC_THRx) is defined by the DATHRx bits. |
| 1 | ALL_THR | All transmit channels are directly loaded by audio peripherals. The DATHRx bits have no effect. |
Bits 0, 1, 2, 3 – ASRCENx ASRC Stereo Channel x Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | DSPx is disabled. |
| 1 | ENABLE | DSPx is enabled. |