4.17.2 Embedded Characteristics

The Power Management Controller provides the following clocks:

Main System Bus Clocks (MCKx)—clock signals that are the root clock of a group of peripherals. They are programmable from a few hundred Hz to the maximum operating frequency of the peripheral group. MCK0 is the main system bus clock associated to all peripherals that are synchronous with the processor.
Processor Clock (CPU_CLK)—can be tuned through a frequency scaler module and automatically switched off when entering the processor in Sleep mode.
Free-Running Processor Clock (FCLK)—the source clock of CPU_CLK. Is not affected when Sleep mode or the frequency scaler is activated.
UHDP Clocks (UHP48M and UHP12M)—required by USB Host Device Port operations.
Peripheral Clocks with independent on/off control, provided to the peripherals. Each peripheral clock is inherited from one of the MCKx clocks.
Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCKx pins.
Generic Clock (GCLK) with controllable division and on/off control, independent of MCKx and CPU_CLK. Provided to selected peripherals. Refer to the table “Peripheral Identifiers” for more details on GCLK availability per peripheral.

The Power Management Controller also provides the following features on clocks: