9.7.5.7 System Interrupts

The Interrupt Status register (I3CC_INTR_STATUS) and PIO Interrupt Status register (I3CC_PIO_INTR_STATUS) are associated with error and status condition reporting. These registers trigger the interrupt signal which is synchronous with the user interface clock.

The triggering of the interrupt line can be disabled by the Interrupt Signal Enable register (I3CC_INTR_SIGNAL_ENABLE) and the PIO Interrupt Signal Register (I3CC_PIO_INTR_SIGNAL_ENABLE). By default, all interrupts are enabled. When any bit of these registers is set to ‘0’, it disables the generation of interrupts in that specific interrupt pin. Thus, the interrupt signal outputs can be controlled by I3CC_INTR_SIGNAL_ENABLE and I3CC_PIO_INTR_SIGNAL_ENABLE.

The interrupt bit is always set in I3CC_INTR_STATUS or I3CC_PIO_INTR_STATUS, irrespective of I3CC_INTR_SIGNAL_ENABLE and I3CC_PIO_INTR_SIGNAL_ENABLE.

The Interrupt Force registers (I3CC_INTR_FORCE and I3CC_PIO_INTR_FORCE) are used for test purposes, and trigger interrupt events individually, without the need to activate the conditions that trigger the interrupt sources. Setting any bit of these registers to ‘1’ triggers the corresponding interrupt, provided the corresponding bit in I3CC_INTR_STATUS_ENABLE or I3CC_PIO_INTR_SIGNAL_ENABLE is set.

I3CC_INTR_STATUS and I3CC_PIO_INTR_STATUS are used to check the true status of the interrupt events which are activated through specific bits in I3CC_INTR_STATUS_ENABLE and I3CC_PIO_INTR_SIGNAL_ENABLE. This register consists of the status of interrupt sources irrespective of disabling in I3CC_INTR_SIGNAL_ENABLE and I3CC_PIO_INTR_SIGNAL_ENABLE. When any bit of I3CC_INTR_STATUS_ENABLE or I3CC_PIO_INTR_SIGNAL_ENABLE is set to ‘0’, it disables the generation of the interrupt in that specific I3CC_INTR_STATUS or I3CC_PIO_INTR_STATUS bit and the interrupt line.

The following figure shows the interrupt generation mechanism in the I3CC.