9.7.5.2 I3C Bus Configuration

The I3CC supports three types of I3C bus configuration, as defined by the MIPI I3C Specification:

• Pure Bus — Only I3C devices present on the bus.
• Mixed Fast Bus — I3C devices and legacy I2C targets without host capability, without clock stretching and with a true I2C 50 ns glitch filter on I3CC_SCL.
• Mixed Slow/Limited Bus — I3C devices and legacy I2C targets without host capability, without clock stretching but without a true I2C 50 ns glitch filter on I3CC_SCL.

In a mixed fast bus configuration, the maximum possible data rate with I3C devices depends on the compliance of the I2C target as defined by the I2C Specification. The maximum data rate as specified in the I3C specification is possible only if all I2C targets have the 50 ns glitch filter.

In the absence of glitch filters or if the presence of a filter is unknown, the maximum data rate is limited to only FM or FM+, even for I3C devices (as per the I3C Specification). I2C targets are not allowed to extend the clock.