4.1.3.1.1 Changing System Frequencies

After ROM code execution, the system clock is set as follows:
  • MAINCK is fed by the main RC oscillator i.e., 12 MHz.
  • CPUPLL is set to 570 MHz.
  • MCK0 is set to CPUPLL/3, i.e., 190 MHz.
  • SYSPLL is set to 378 MHz.
  • MCK1 is set to SYSPLL/2, i.e., 189 MHz.
  • MCK5 is set to SYSPLL/2, i.e., 189 MHz.
  • MCK6 is set to SYSPLL/2, i.e., 189 MHz.
  • MCK7 is set to SYSPLL/4, i.e., 94.5 MHz.

This is illustrated in the following figure.

Figure 4-2. PMC ROM Code Configuration

To avoid any overclocking during system clock modification, it is recommended to change system frequencies in two steps.

The first step leads to a known and basic intermediate state where all clocks are in a low-frequency range.

For example, the following sequence can be performed:
  1. Set MCK0 to MAINCK, i.e., 12 MHz.
  2. Set MCK1 to MCK0, i.e., 12 MHz.
  3. Set MCK4 to MCK0, i.e., 12 MHz.
  4. Set MAINCK to Crystal Oscillator, typically 24 MHz. MCK0, MCK1 and MCK4 then run at 24 MHz.
  5. Set CPUPLL to 1 GHz.
  6. Set SYSPLL to 400 MHz.

This intermediate state is illustrated in the following figure.

Figure 4-3. PMC Intermediate Configuration

The second step leads to the final expected state.

Perform the following sequence:
  1. Set MCK0 to CPUPLL/5, i.e., 200 MHz.
  2. Set MCK1 to SYSPLL/2, i.e., 200 MHz.
  3. Set MCK4 to SYSPLL, i.e., 400 MHz.

The final state is illustrated in the following figure.

Figure 4-4. PMC Final Configuration