4.5.4.2.4 Main System Bus Clock (MCK0) Failure Detection Reset

The system embeds a Main System Bus clock (MCK0) frequency monitor that is located in the PMC. It can be enabled by setting CKGR_MOR.BMCKRST.

The Main System Bus clock (MCK0) Failure Detection reset is done when the frequency monitor detects a failure and RSTC_MR.SYSFEN=1. This reset lasts three MD_SLCK cycles.

When RSTC_MR.SYSFEN=0, the Main System Bus clock (MCK0) fault has no impact on the RSTC.

During a Main System Bus clock (MCK0) Failure Detection reset, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on the value of RSTC_MR.ERSTL.

When the Main System Bus clock (MCK0) failure generates a VDDCORE reset, PMC_SR.MCKMON is automatically cleared by the peripheral and core reset.

Figure 4-12. Main System Bus Clock (MCK0) Failure Detection Reset Timing Diagram