11.1.11.4.1 Introduction
To optimize the device power consumption in Low-Power modes ULP0 and ULP1, the embedded
memories of the following peripherals can be switched to a Low-Power state:
- I3CC
- DSI
- EHCI
- UDPHSB
- UDPHSA
- SDMMC2
- SDMMC1
- SDMMC0
- LCDC
- GMAC1
- GMAC0
- GPU2DC
- UDDRC
- ASRC
- NFC
The embedded Low-Power state is controlled independently for each peripheral by enabling/disabling the associated peripheral clock. The same behavior applies when the system switches to ULP1. The Special Function Registers SFR_MEMPOWER, SFR_CLEAR_ONLY_SD_CFG and SFR_DISABLE_SD_CFG define the automatic switching policy.
Four memory power states are supported:
- Normal
- Light Sleep
- Deep Sleep
- Shutdown
These four states allow a tradeoff between data retention, power consumption and wake-up delay. See the following table.
| Memory Power State | Data Retention | Power Consumption | Wake-Up Delay |
|---|---|---|---|
| Normal (Running) | Yes | – | N/A |
| Light Sleep | Yes | + | +++ |
| Deep Sleep | Yes | ++ | ++ |
| Shutdown | No | +++ | + |
The control of the memories Low-Power states offers the following options:
- The Low-Power state entry can be totally disabled for all memories.
- The Low-Power state entry and exit can be automatically performed when a peripheral clock is enabled or disabled, or when a Low-Power mode is entered or exited.
- The Low-Power state level (Light Sleep, Deep Sleep or Shutdown) can be configured.