4.8.7.7 SHDWC Interrupt Mask Register
| Name: | SHDW_IMR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WKUP5 | WKUP4 | WKUP3 | WKUP2 | WKUP1 | WKUP0 | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5 – WKUPx Wake-up x Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The corresponding interrupt is not enabled. |
| 1 |
The corresponding interrupt is enabled. |