6.3.7.5 LVDSC Analog Control Register

This register can only be written if WPEN is cleared in LVDSC_WPMR.

Name:	LVDSC_ACR
Offset:	0x14
Reset:	0x00000009
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
						PREEMP_CLK1[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	23	22	21	20	19	18	17	16
		PREEMP_A3[2:0]				PREEMP_A2[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	15	14	13	12	11	10	9	8
		PREEMP_A1[2:0]				PREEMP_A0[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	DCBCAL			DCBIAS[4:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	1	0	0	1

Bits 26:24 – PREEMP_CLK1[2:0] Pre-Emphasis Control for CLK LVDS Lane


PREEMP_CLK	C_load (pF)	G_preemp
100	5	1.2
101		2.4
110		3.6
111		4.8

Bits 8:10, 12:14, 16:18, 20:22 – PREEMP_Ax Pre-Emphasis Control for Ax LVDS Lane


PREEMP_Ax	C_load (pF)	G_preemp
100	5	1.2
101		2.4
110		3.6
111		4.8

Bit 7 – DCBCAL DC Bias Calibration

Refer to the section “Electrical Characteristics”.

Value	Description
0	Configure DC bias with the DCBIAS field.
1	Configure DC bias with the factory calibration value.

Bits 4:0 – DCBIAS[4:0] Common DC Bias Control for LVDS Lanes

The nominal trimming to program is LVDSC_ACR.DCBIAS = 9 to reach a typical ±350 mV DC differential output amplitude for a 100-ohm differential load. This field is used only when DCBCAL is set to 0.