7.4.7.13 SPDIF Receiver Fault Injection Register
This register can only be written if the FIRDIS bit is cleared.
| Name: | SPDIFRX_FIR |
| Offset: | 0x94 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRDIS | FPARE | F4 | F3 | F2 | F1 | F0 | |||
| Access | R/W | W | W | W | W | W | W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:8 – FIKEY[23:0] Fault Injection Access Key
| Value | Name | Description |
|---|---|---|
| 0x534649 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 7 – FIRDIS Fault Injection Register Disable
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | ACTIVE | Disables the fault injection until the next hardware reset. The command is valid only if the flag SPDIFRX_WPSR.SEQE=0 and the other bits are cleared (F0=F1=F2=F3=F4=FPARE=0). |
Bit 5 – FPARE Single Fault for SPDIFRX Configuration Register
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | INJECT_CLEAR | Injects a single fault on the configuration register if the SPDIFRX is disabled (for security reason), the flag SPDIFRX_WPSR.PARE raises and the flag SPDIFRX_ISR.SECE =1. Clears the fault if it has been previously injected. |
Bit 4 – F4 Single Fault for SPDIFRX Write Protection Mode Register (SPDIFRX_WPMR.WPCREN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag SPDIFRX_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety for the SPDIFRX_WPMR.WPCREN bit if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The SPDIFRX remains in the same state, the flag SPDIFRX_ISR.SECE=1 and the flag SPDIFRX_WPSR.SDEE=1. |
Bit 3 – F3 Single Fault for SPDIFRX Write Protection Mode Register (SPDIFRX_WPMR.WPITEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag SPDIFRX_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety for the SPDIFRX_WPMR.WPITEN bit if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The SPDIFRX remains in the same state, the flag SPDIFRX_ISR.SECE=1 and the flag SPDIFRX_WPSR.SDEE=1. |
Bit 2 – F2 Single Fault for SPDIFRX Write Protection Mode Register (SPDIFRX_WPMR.WPEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag SPDIFRX_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety for the SPDIFRX_WPMR.WPEN bit if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The SPDIFRX remains in the same state, the flag SPDIFRX_ISR.SECE=1 and the flag SPDIFRX_WPSR.SDEE=1. |
Bit 1 – F1 Single Fault for SPDIFRX Mode Register (SPDIFRX_MR.RXDIRECT)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag SPDIFRX_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety for the SPDIFRX_MR.RXDIRECT bit if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The SPDIFRX remains in the same state, the flag SPDIFRX_ISR.SECE=1 and the flag SPDIFRX_WPSR.SDEE=1. |
Bit 0 – F0 Single Fault for SPDIFRX Mode Register (SPDIFRX_MR.RXEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag SPDIFRX_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety for the SPDIFRX_MR.RXEN bit if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The SPDIFRX remains in the same state, the flag SPDIFRX_ISR.SECE=1 and the flag SPDIFRX_WPSR.SDEE=1. |