7.2.7.21 I2SMCC Write Protection Status Register

Name: I2SMCC_WPSR
Offset: 0xE8
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
       SWETYP[1:0] 
Access RR 
Reset 00 
Bit 2322212019181716 
 WPVSRC[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 WPVSRC[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
  HWERRWSALIGNERRSDEESWEPAREPADERRWPVS 
Access RRRRRRR 
Reset 0000000 

Bits 25:24 – SWETYP[1:0] Software Error Type (cleared on read)

ValueNameDescription
0 READ_WO A write-only register has been read.
1 WRITE_RO A write access has been performed on a read-only register.
2 UNDEF_RW Access to an undefined address.

Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source

When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.

Bit 6 – HWERR Hardware Error in Client Mode and Direct Access Transfer (cleared on read)

ValueDescription
0 No abnormal underflow in transmitter detected In Client mode and direct access with ASRC.
1

Abnormal underflow detected in transmitter when configured in Client mode and direct access with ASRC. The transmitter is automatically re-initialized to continue streaming the audio samples from ASRC. The error may be created from an unexpected disable of the direct access mode in ASRC or from an abnormal condition on the I2SMCC_CK/WS pins.

Bit 5 – WSALIGNERR WS Alignment Error (cleared on read)

ValueDescription
0 No internal nonalignment that could result from abnormal conditions on I2SMCC_WS/CK input pins.
1

In Client mode (I2SMCC_WS/CK are inputs), an abnormal alignment has been detected between internal WS and CK signals. This may result from a glitch on I2SMCC_CK or I2SMCC_WS drivers or the absence of voltage hysteresis management on the pad buffer driving the internal CK clock pin. This flag may also be asserted when the audio codec providing WS/CK generates an unexpected misalignment.

Bit 4 – SDEE Single or Dual Event Error (cleared by reconfiguring the faulty registers or by clearing the error via I2SMCC_FIR)

If a single error event occurred, the error is filtered and has no effect on I2SMCC.
ValueDescription
0 No single or dual error detected in I2SMCC_CR.RXEN/RXDIS, I2SMCC_CR.TXEN/TXDIS, I2SMCC_CR.CLKEN/CLKDIS, I2SMCC_MRB.RXDIRECT/TXDIRECT, I2SMCC_WPMR.WPCFEN, I2SMCC_WPMR.WPITEN, I2SMCC_WPMR.WPCTEN.
1 Single or dual error detected in I2SMCC_MRA.I2SMCC_CR.RXEN/RXDIS, I2SMCC_CR.TXEN/TXDIS, I2SMCC_CR.CLKEN/CLKDIS, I2SMCC_MRB.RXDIRECT/TXDIRECT, I2SMCC_WPMR.WPCFEN, I2SMCC_WPMR.WPITEN, I2SMCC_WPMR.WPCTEN.

Bit 3 – SWE Software Control Error (cleared on read)

ValueDescription
0 No software error has occurred since the last read of I2SMCC_WPSR.
1 A software error has occurred since the last read of I2SMCC_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0).

Bit 2 – PARE Internal Single Error Detection Configuration Registers

ValueDescription
0 No internal single error has been detected on configuration registers since the last read of I2SMCC_WPSR.
1 An internal single error has been detected. This flag is set under abnormal operating conditions or if the fault injection I2SMCC_FIR.FPARE is performed (only available if I2SMCC RX and TX are both disabled). I2SMCC_MRA/MRB/IMRA/IMRB and WPMR registers are monitored with a single error detection for each register.

Bit 1 – PADERR WS or SCK Pad Error (cleared on read)

An error occurs when there is a difference between the data read at the output of the pad buffer and the internal value generated by the I2SMCC. This error affects the functional safety of I2S transfers. The root cause can be an erroneous IO multiplexing configuration, a transistor failure, an external short circuit, etc. To verify the PADERR detection mechanism, it is possible to intentionally trigger an error by applying a bad configuration (same direction but stuck-at output values) in the IO multiplexing related to I2SMCC_WS or I2SMCC_CK and starting an I2S transfer.
ValueDescription
0 No error has been detected on I2SMCC_WS and I2SMCC_CK pad outputs since the last read of I2SMCC_WPSR.
1 Two successive erroneous samplings of WS pad output or abnormal number of clock edges have been detected on I2SMCC_CK pad output during the transmission of 1 audio sample. The event occurred since the last read of I2SMCC_WPSR.

Bit 0 – WPVS Write Protection Violation Status

ValueDescription
0 No write protection violation has occurred since the last read of the I2SMCC_WPSR.
1 A write protection violation has occurred since the last read of the I2SMCC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.