7.2.7.19 I2SMCC Fault Injection Register
This register can only be written if FIRDIS is cleared.
All bits are write-only except FIRDIS.
| Name: | I2SMCC_FIR |
| Offset: | 0x80 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRDIS | FPARE | F5 | F4 | F3 | F2 | F1 | F0 | ||
| Access | R/W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:8 – FIKEY[23:0] Fault Injection Access Key
| Value | Name | Description |
|---|---|---|
| 0x494649 | PASSWD |
Writing any other value in this field aborts the write operation. |
Bit 7 – FIRDIS Fault Injection Register Disable
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect |
| 1 | ACTIVE | Disables the fault injection until the next hardware reset. The command is valid only if the I2SMCC_WPSR.PARE=0 and the other bits are cleared (F0=F1=F2=F3=F4=FPARE=0). |
Bit 6 – FPARE Single Fault for I2SMCC Configuration Register
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect |
| 1 | INJECT | Injects a single fault on configuration register if the I2SMCC receiver and transmitter are both disabled (for security reasons), the flag I2SMCC_WPSR.PARE rises and the flag I2SMCC_ISRB.WERR =1. To clear the fault, all the fields of the corresponding Configuration registers must be reconfigured. For I2SMCC_IMR, the clear is performed by writing a ‘1’ into all the fields of I2SMCC_IDR. Thus the functional value must be reloaded by writing in I2SMCC_IER. |
Bit 5 – F5 Single Fault for I2SMCC Write Protection Enable (I2SMCC_WPMR.WPCFEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on I2SMCC_CR.WPCFEN if 0x494649 (“IFI” in ASCII) is written in FIKEY at the same time and if the flag I2SMCC_FIR.FIRDIS=0. The I2SMCC remains in the same state, the flag I2SMCC_ISRB.WERR=1 and the flag I2SMCC_WPSR.SDEE=1. |
Bit 4 – F4 Single Fault for I2SMCC Transmitter Direct Access Enable (I2SMCC_CR.TXDIRECT)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on I2SMCC_CR.TXDIRECT if 0x494649 (“IFI” in ASCII) is written in FIKEY at the same time and if the flag I2SMCC_FIR.FIRDIS=0. The I2SMCC remains in the same state, the flag I2SMCC_ISRB.WERR=1 and the flag I2SMCC_WPSR.SDEE=1. |
Bit 3 – F3 Single Fault for I2SMCC Receiver Direct Access Enable (I2SMCC_CR.RXDIRECT)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on I2SMCC_CR.RXDIRECT if 0x494649 (“IFI” in ASCII) is written in FIKEY at the same time and if the flag I2SMCC_FIR.FIRDIS=0. The I2SMCC remains in the same state, the flag I2SMCC_ISRB.WERR=1 and the flag I2SMCC_WPSR.SDEE=1. |
Bit 2 – F2 Single Fault for I2SMCC Transmitter Enable (I2SMCC_CR.TXEN/TXDIS)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on I2SMCC_CR.TXEN/TXDIS if 0x494649 (“IFI” in ASCII) is written in FIKEY at the same time and if the flag I2SMCC_FIR.FIRDIS=0. The I2SMCC remains in the same state, the flag I2SMCC_ISRB.WERR=1 and the flag I2SMCC_WPSR.SDEE=1. |
Bit 1 – F1 Single Fault for I2SMCC Clock Enable (I2SMCC_CR.CLKEN/CLKDIS)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on I2SMCC_CR.CLKEN/CLKDIS if 0x494649 (“IFI” in ASCII) is written in FIKEY at the same time and if the flag I2SMCC_FIR.FIRDIS=0. The I2SMCC remains in the same state, the flag I2SMCC_ISRB.WERR=1 and the flag I2SMCC_WPSR.SDEE=1. |
Bit 0 – F0 Single Fault for I2SMCC Receiver Enable (I2SMCC_CR.RXEN/RXDIS)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on I2SMCC_CR.RXEN/RXDIS if 0x494649 (“IFI” in ASCII) is written in FIKEY at the same time and if the flag I2SMCC_FIR.FIRDIS=0. The I2SMCC remains in the same state, the flag I2SMCC_ISRB.WERR=1 and the flag I2SMCC_WPSR.SDEE=1. |