7.3.8.10 Register Write Protection
To prevent any single software error from corrupting SSC behavior, certain registers in the address space can be write-protected by setting the WPEN, WPITEN and WPRCEN bits in the SSC Write Protection Mode Register (SSC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SSC Write Protection Status Register (SSC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the SSC_WPSR.
The following registers can be write-protected with the SSC_WPMR.WPEN bit:
- SSC Clock Mode Register
- SSC Receive Clock Mode Register
- SSC Receive Frame Mode Register
- SSC Transmit Clock Mode Register
- SSC Transmit Frame Mode Register
- SSC FIFO Mode Register
- SSC Direct Access Mode Register
- SSC Receive Compare 0 Register
- SSC Receive Compare 1 Register
The following registers can be write-protected
with the SSC_WPMR.WPITEN bit:
The following register can be write-protected
with the SSC_WPMR.WPCREN bit: