37.14 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| CCL0 | 0x4482E000 |
APB: CLKMSK[1] MASK20 | PCHCTRL[36] |
42 STATUS1 PERID10 |
Generators: LUTOUT0: CHANNEL[83] LUTOUT1: CHANNEL[84] LUTOUT2: CHANNEL[85] LUTOUT3: CHANNEL[86] Users: LUTIN0: USER[53],Resynch LUTIN1: USER[54],Resynch LUTIN2: USER[55],Resynch LUTIN3: USER[56],Resynch |
PD_CORE_SW | ||
| CCL1 | 0x44830000 |
APB: CLKMSK[1] MASK21 | PCHCTRL[37] |
43 STATUS1 PERID11 |
Generators: LUTOUT0: CHANNEL[87] LUTOUT1: CHANNEL[88] LUTOUT2: CHANNEL[89] LUTOUT3: CHANNEL[90] Users: LUTIN0: USER[57],Resynch LUTIN1: USER[58],Resynch LUTIN2: USER[59],Resynch LUTIN3: USER[60],Resynch |
PD_CORE_SW |