35.6 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| CAN0 | 0x4402E000 |
35 : INT0 36 : INT1 37 : BERR/DBG |
AHB: CLKMSK[0] MASK23 | PCHCTRL[6] |
17 STATUS0 PERID17 |
PD_CORE_SW | ||
| CAN1 | 0x44030000 |
38 : INT0 39 : INT1 40 : BERR/DBG |
AHB: CLKMSK[0] MASK24 | PCHCTRL[7] |
18 STATUS0 PERID18 |
PD_CORE_SW |