38.2 Features

Up to 12-bit resolution of the numerical output, signed or unsigned (Higher resolutions possible with oversampling).

  • Signed/Unsigned results
  • Left or Right aligned result
  • Fractional or integer results
  • External analog inputs:
    • Up to 12 single ended input channels (AIN[11:0])
    • Or up to 3 differential inputs channels (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5), plus 6 single ended input channels (AIN[11:6])

  • Internal inputs:

    • VDDCORE internal analog channel AIN12
    • IVREF 1.2v, internal analog channel AIN14
  • Up to 16 trigger sources, off-chip hardware or on-chip hardware or software generated per analog input channel.
  • Edge or level active triggering modes, generating single conversions or bursts of conversions.
  • A scan trigger to start a scan cycle which can individually include or not include any of the analog inputs.
  • Any of the 16 trigger sources or the scan triggers can be assigned to individual analog input channels.
  • The scan trigger itself can select any of the 16 trigger sources as its own source.
  • Programmable sampling time, CORCTRL.SAMC.
  • Each analog input/channel output register can be read from a general dedicated output register (Write to the CORDYID and CHRDYID registers and then reads the CHRDYDATA register).
  • 16sample deep FIFO supporting all channels.
  • Digital Comparator for monitoring output values in relation to user-specified ADC result threshold.
  • Digital filter; providing averaging/oversampling for increased noise immunity and are assignable to any analog input.