3.4.1 SPI Clock

Clarifications regarding the SPI clock have been made in the Operation - Slave Mode and Operation - Slave Mode - Buffer Mode sections. Functional changes are shown in bold.

25.3.2.2 Slave Mode

In Slave mode, the SPI peripheral receives the SPI clock and Slave Select from a Master. Slave mode supports three operational modes: One Normal mode and two configurations for the Buffered mode. In Slave mode, the control logic will sample the incoming signal on the SCK pin. To ensure correct sampling of this clock signal, the minimum low and high periods must each be longer than two peripheral clock cycles.

25.3.2.2.3 Buffer Mode

To avoid data collisions, the SPI peripheral can be configured in Buffered mode by writing a ‘1’ to the Buffer Mode Enable (BUFEN) bit in the Control B (SPIn.CTRLB) register. In this mode, the SPI has additional interrupt flags and extra buffers. The extra buffers are shown in Figure 25-1. There are two different modes for the Buffer mode, selected with the Buffer mode Wait for Receive (BUFWR) bit. The two different modes are described below with timing diagrams.

Note: When operating as a slave in Buffered mode and the SPI clock is close to maximum frequency, the slave may not be able to set up data in time for the first sample edge during back-to-back transfers. Refer to the Electrical Characteristics - SPI section for details.