3.4.2 Implementation Example for DDR3

Note that the following design, which aims at minimizing the area covered by the SDRAM interface implementation and at keeping the layer stack to a minimum of 4 layers, does not fully comply with the recommendations set forth in 4.2 Good Practices and must be considered as experimental.

Figure 3-6. DDR3 Routing on Top Layer

Figure 3-7. DDR3 Routing on Bottom Layer

In the board used as example for this application note, the SDRAM signals routed on the bottom layer use the VDDIOM power plane as reference.

On both the top and the bottom layers, signals are impedance-matched and length-matched. Differential signals are routed accordingly, with a differential impedance of 100 ohms (50 ohms for single-ended signals).

Special care was taken when designing the SAM9X75 stand-alone MPU package ball-out to ease an optimal routing path for the SDRAM memory.

The same rules must be applied to all other high speed interfaces, like MII/RMII/RGMII, QSPI, SDMMC, MIPI, LVDS and USB.