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PIC18F06/16Q40 Silicon Errata and Data Sheet Clarifications
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PIC18F06Q40
PIC18F16Q40
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1
Silicon Errata Issues
1.3
Module: Inter-Integrated Circuit (I
2
C)
Introduction
1
Silicon Errata Issues
1.1
Module: Analog-to-Digital Converter with Computation (ADCC)
1.2
Module: Oscillator (OSC)
1.3
Module: Inter-Integrated Circuit (I
2
C)
1.3.1
The I2CxADR0/1/2/3 Registers Have Incorrect Reset Value
1.3.2
The I
2
C Start and/or Stop Flags May Be Set When I
2
C Is Enabled
1.3.3
MDR Bit Is Not Cleared after Bus Time-Out
1.3.4
Bus Time-Out Not Detected Properly When External Host Clock Stretches
1.3.5
Clock Stretch Disable Not Working Properly
1.3.6
Bus Time-Out Causes False Start/Stop
1.3.7
CSTR Bit Is Not Cleared after Bus Time-Out
1.3.8
Operating in Multi-Host Mode Will Cause Bus Failures
1.4
Module: Universal Asynchronous Receiver Transmitter (UART)
1.5
Module: Signal Measurement Timer (SMT)
1.6
Module: PIC18 Core
1.7
Module: Low-Voltage In-Circuit Serial Programming™ (LVP)
1.8
Module: Instruction Set
2
Data Sheet Clarifications
3
Appendix A: Revision History
Microchip Information
1.3 Module: Inter-Integrated Circuit (I
2
C)
