1.1.1 ADC Conversion May Not Complete

An ADC conversion may not complete under these conditions:
  1. When FOSC is greater than 8 MHz and it is the clock source used for the ADC converter.

  2. The ADC is operating from its dedicated ADCRC oscillator and the device is not in Sleep mode (at any FOSC frequency). When this occurs, the ADC Interrupt Flag (ADIF) does not get set, the GO/DONE bit does not get cleared, and the conversion result does not get loaded into the ADRESH and ADRESL result registers.

Work around

Method 1:

Select the system clock, FOSC, as the ADC clock source and reduce the FOSC frequency to 8 MHz or less when performing ADC conversions.

Method 2:

Select the dedicated ADCRC oscillator as the ADC conversion clock source and perform all conversions with the device in SLEEP

Method 3:

This method is provided if the application cannot use Sleep mode and requires continuous operation at frequencies above 8 MHz. This method requires early termination of an ADC conversion. Provide a fixed time delay in software to stop the ADC conversion manually, after all 10 bits are converted, but before the conversion would complete automatically. The conversion is stopped by clearing the GO/DONE bit in software, and must be cleared during the last ½ TAD cycle, before the conversion would have completed automatically.

In Figure 1-1, 88 instruction cycles will be required to complete the full conversion. Each TAD cycle consists of 8 TCY periods. A fixed delay is provided to stop the A/D conversion after 86 instruction cycles and terminate the conversion at the correct time.

Note: The exact delay time will depend on the TAD divisor (ADCS) selection. The TCY counts shown in Figure 1-1 apply to this example only. Refer to Table 1-1 for examples of the required delay counts for other configurations.
Figure 1-1. Instruction Cycle Delay Calculation Example
Table 1-1. Instruction Cycle Delay Counts by TAD Selection
TADInstruction Cycle Delay Counts by TAD Selection
FOSC/64172
FOSC/3286
FOSC/1643

Code Example of Instruction Cycle Delay

BSF     ADCON0, ADGO     ; Start ADC Conversion
                         ; Provide 86 instruction cycle delay here
BCF     ADCON0, ADGO     ; Terminate the conversion manually
MOVF    ADRESH, W        ; Read the conversion result

Affected Silicon Revisions

A1A2A3
X