6.1 Device Addressing

Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read or write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its own unique address so the master can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type identifier ‘1010’ (Ah) for the main EEPROM access or ‘1011’ (Bh) for Security register and Write Protection register access is required in bits 7 through 4 of the device address byte (see Table 6‑1).

Following the 4‑bit device type identifier are the slave address bits, A2 and A1. The value that the AT24CSW04X/AT24CSW08X will ACK to is preprogrammed in each device. Unique ordering codes are available for each of the four (AT24CSW04X) or two (AT24CSW08X) possible slave combinations. The slave address preprogrammed in the device is embedded in the base part number as shown in Table 6-3 and Table 6-4.

The AT24CSW04X/AT24CSW08X contains a 32‑byte Security Register, organized as 2 pages of 16 bytes each. This register contains a factory‑programmed unique 128‑bit serial number in the lower 16 bytes. The upper 16 bytes are user‑programmable and can (later) be permanently write‑protected (see Write Operations in the Security Register).

Access to the Security register memory location is similar to the EEPROM region with the exception that the device address word must begin with '1011' (Bh). The behavior of the hardware address bits (A2, A1) remains the same as during an EEPROM addressing sequence (see Table 6-3 and Table 6-4). While the lower order 16 bytes of the Security register are read‑only, the device will ACK if this bit is a logic '0'. To read from the Security register, refer to Read Operations in the Security Register and for writing refer to Write Operations in the Security Register.

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24CSW04X/AT24CSW08X will return an ACK. If a valid comparison is not made, the device will NACK.

For all operations except the current address read, a word address byte must be transmitted to the device immediately following the device address byte. The word address byte contain a 9-bit (in the case of the AT24CSW04X) or 10-bit (in the case of the AT24CSW08X) memory array word address and is used to specify which byte location in the EEPROM to start reading or writing. Refer to Table 6-5 to review these bit positions.

When accessing the Security register, it is required that the A7 and A6 bits of the word address be set to '10' respectively. These bits are at a higher order address range than what is needed to address the 32‑byte space (A4 through A0). It is recommended that all address bits that fall outside the address range that do not have other requirements be set to a logic '0'.