10.3 Write Operations in the Security Register

The Security register supports byte writes, page writes, and partial page writes in the upper 16 bytes of the region. Page writes and partial page writes in the Security register have the same page boundary restrictions and behavior as they do in the EEPROM region (see Write Operations).

Writing in the Security register requires beginning the device address byte with 1011b(Bh), matching the hardware address bits (A2, A1, A0) to the corresponding value determined by the ordering code (see Table 6-2), and sending a logic ‘0’ in the Read/Write Select bit. The device will ACK this sequence.

Following the device address byte, bits A7 and A6 of the word address byte must be set to 10b regardless of the intended address being written. Refer to Table 6-3 for detailed requirements on these bits. Figure 10-2 is an example of a byte write operation in the Security register.

Figure 10-2. Byte Write in the Security Register

Note: # indicates the hardware address value which is managed by the ordering code of the device (see Table 6-2).

The user-programmable portion of the Security register can be permanently inhibited from future writing with the Lock command. The status of the Lock state can be determined by sending a subset of the Lock command.